"Are we meeting the specific goals this year? Not to the aggressive levels we've set," Abhi Talwalkar, general manager of Intel's Enterprise Platform Group, said while answering questions after a speech at the Intel Developer Forum here.
Paul Otellini, president, Intel
Despite the admission, Talwalkar also said Itanium is strong and meeting its long-term goals.
In large-scale servers, Itanium server revenue has been doubling or tripling, compared to year-earlier periods, while increasing tenfold for top-end machines with 16 or more processors. In addition, the number of dual- and four-processor Itanium-based server models has increased from 20 in 2002 to 70 this year, while the number of systems with eight or more Itanium processors has increased from five to 20 during the same period, he said.
To try to boost sales, Intel is promoting pilot programs to let potential customers test Itanium servers in the hope that they'll then commit to the technology, Talwalkar said in interview.
Slow start notwithstanding, Intel remains committed to Itanium. Earlier Tuesday, Talwalkar demonstrated a four-processor server that uses the next-generation Montecito model in the Itanium family, due out in 2005.
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And in his speech, Talwalkar showed a plan for a faster Montecito code-named Montvale, due to arrive by the end of 2006. In addition, there will be a low-voltage version of Montvale.
There is a place for both Xeon and Itanium, he said. "We believe the dual-architecture approach is the best approach to meet the diverse needs" of corporate buyers, he said.
But he also acknowledged the difficulty caused by the decision to upgrade Xeon with 64-bit extensions, a feature that lets it address more memory and which previously was one of the main advantages Itanium had over Xeon.
"I would be remiss to say the impact was zero, but the impact was mostly noise and confusion," Talwalkar said of the decision, referred to as EM64T. "It set us back a few months, I think, with the general audience."
Illuminata analyst Jonathan Eunice offered an interpretation of Talwalkar's words: "The EM64T thing knocked them for a loop," he said. "They should have expected that, but planning cycles and announcement cycles aren't always synchronized."
Intel was forced to announce EM64T earlier than it hoped, because rival Advanced Micro Devices was stealing too much thunder with its own version of the technology, AMD64, which went on sale with the Opteron processor in 2003, Eunice said.
"The AMD stuff was just getting too hot and too visible. Really good customers were getting too interested," Eunice said.
The next Itanium
The next addition to the Itanium family will be an Itanium 2 that runs faster by boosting on-board cache memory from the current 6MB to 9MB. It will arrive by the end of the year, Talwalkar said in a meeting with reporters--a little late, according to sources who said Intel had hoped to unveil it this week.
Power consumption and its corresponding waste heat are another challenge. Coming technology such as demand-based switching--which slows down processors during brief lulls--will address some current power problems, Talwalkar said, but "it's not enough." However, he added, "we've got other things that are driving a significant shift (toward) far better performance-per-watt capability in the coming future."
Intel deserves credit for being candid with customers even when the news doesn't reflect well on the company, Eunice said. "If you're telling people how it is, that's a benefit. These people depend on this technology," he said.
Intel President Paul Otellini defended the Itanium program in a meeting with reporters Tuesday. "This part of the market is strategically important," he said, and building chips for high-performance machines lets Intel develop new features that later can be added to lower-cost processors.
New chips revealed
Intel also revealed code names and schedule details for several new processors, though conspicuously absent was a name for a dual-core Xeon. Among the schedule details:
For multiprocessor Xeon servers--those with four or more processors--Intel announced a new model code-named Cranford, due out in the first half 2005. It will have less high-speed cache memory than the previously announced Potomac model coming at the same time, making it better for price-conscious buyers, Talwalkar said.
Succeeding Cranford and Potomac in 2005 or 2006 will be Tulsa, the first dual-core Xeon for multiprocessor servers. Those three chips will be the first multiprocessor models to support EM64T, Talwalkar said.
The next-generation multiprocessor Xeon, coming in 2006 or 2007, is code-named Whitefield. It will use the "Common Platform Architecture," a technology that lets Xeon and Itanium servers share the same socket, electrical communications, memory interface, chipsets and other components.
Talwalkar described several lower-end Itanium models for dual-processor servers. As Itanium progresses from the imminent Itanium 2 9MB cache product to Montecito to Montvale to Tukwila, corresponding versions of those chips are planned for dual-processor servers. Those versions are code-named Fanwood, Millington, DP Montvale and Dimona, respectively, Talwalkar said, and all those chips also will be released in low-voltage versions.
A dual-processor Xeon code-named Irwindale will debut in 2005. It's a new version of the current "Nocona" version of Xeon that boosts cache memory from 1MB to 2MB, he said.
By 2006, Intel will begin offering a feature code-named Silvervale Technology (ST) that will make it easier to run multiple independent operating systems on Xeon or Itanium servers. The technology uses the same interface as the Vanderpool Technology (VT) that will bring a similar feature to PCs, meaning that software companies such as Microsoft or VMware supporting the technology won't have to write different versions of their products for ST and VT, Talwalkar said.
Talwalkar also demonstrated a faster memory technology called FBD--short for "fully buffered DIMM" (double inline memory module)--that will debut "in the first part 2006" in dual-processor servers, he said. FBD, which grafts onto existing DDR2 (Double Data Rate 2) memory chips, transmits data to and from memory modules using a serial interface that can operate at higher speeds than the prevailing parallel method.
Serial interfaces transmit streams of data at high speeds that are collected in a memory storage area called a buffer. By comparison, parallel interfaces transmit data in lockstep across several signal paths, but synchronization issues make it harder to improve. Serial technologies such as universal serial bus and serial ATA hard drives have been replacing parallel interfaces in PCs in recent years.