The company plans to describe the new high-end Itanium chip at its Developer Forum next month. The chip will include as many as 16 processors on a single slice of silicon.
So-called multicore designs that include several processors on the same chip are an increasingly popular way to use the ever-larger amounts of circuitry that advanced manufacturing processes permit, but other companies are slightly ahead of Intel in the multicore business. IBM's Power4 chip uses two cores as will new high-end chips from Sun Microsystems and Hewlett-Packard, but the Tanglewood design appears to have room for growth well beyond that.
"The multicore approach to building processors is a natural way of taking advantage of Moore's Law," Insight 64 analyst Nathan Brookwood said, referring to the rule of thumb that predicts rapid doubling of how many circuitry elements (called transistors) can fit onto a processor.
A design that extends as far as 16 cores telegraphs Intel's plans far into the future. "Intel needs to be able to demonstrate there's a road map that's going to keep that up. IBM is out there peddling its road map, Sun is out there peddling its road map," Brookwood said. Itanium got off to a rocky start, but Brookwood said Intel has been able to release new designs more consistently now.
Fitting multiple processors on a single silicon slice, called a die, is difficult with large processors such as today's Itanium 2 models. But Brookwood said it's feasible in future generations, if processors share the high-speed cache memory that today takes up much of the current Itanium's real estate.
Intel's Itanium line is a 64-bit design geared for high-end servers that need to address vast amounts of memory and keep processing glitches from corrupting data. Its chief competitors are IBM's Power products, Sun's UltraSparc line and Advanced Micro Devices' Opteron; Hewlett-Packard is gradually phasing out its PA-RISC line in favor of Itanium.
Intel has conquered most of the low-end server market with its Xeon processor family, which, unlike Itanium, is a variant of its Pentium line and can easily run the same software. To bring Itanium into less-expensive machines, Intel plans to release another Itanium processor that's code-named Deerfield.
Deerfield is scheduled to debut Sept. 8, sources close to the company said. According to Intel product plans from July, Deerfield will cost $744, substantially below the price of Intel's other Itanium 2 chips, which range from $1,338 to $4,226.
Improving how many instruction threads a chip can handle simultaneously is another area chip designers are tackling. Intel's Xeon and Pentium line have basic abilities to run two threads, and Intel is looking at ways to add more threads on server chips, other sources have said. IBM's Power5, coming in 2004, will permit each core to run two threads, and Sun is aggressively pushing multithreading. Itanium currently lacks multithreading, but Tanglewood will include some features for the technology, according to the sources.
Intel expects Tanglewood not to consume more electrical power than current Itanium processors, the sources said, an important feature that would make it easier to design servers without the overheating that causes data corruption and crashes.
The arrival date of Tanglewood is unclear, though it could come as soon as 2006, the year after the dual-core "Montecito" member of the Itanium family is scheduled for release. Intel has extended the current Itanium 2 designs by adding more cache memory this year and in 2004, but that approach isn't on current plans for Montecito, according to the sources.
Brookwood said it's possible that Tanglewood would start with a four-core design that's built with a 90-nanometer manufacturing process, then move to eight- and 16-core designs with a later 65-nanometer process.
A 16-core design isn't totally unprecedented for the Santa Clara, Calif.-based chipmaker, Brookwood added: Intel sells a network processor with 16 cores today.
Sun's Niagara processor, due in 2005, will have eight cores when it's released, but those cores are smaller, because they lack the complicated circuitry for running a single "thread" of instructions as fast as possible. Sun plans to launch a higher-end multicore chip after Niagara that will feature both the multicore design and fast individual thread performance.
Along with the new Itanium, Intel will also discuss "Tiano," a new version of the BIOS (basic input-output system) for servers. The BIOS, which records system settings and acts as an interface between a computer's hardware and software, is one of the oldest, least evolved elements of a computer.
A few years ago, a number of companies began to work on the Extensible Firmware Interface (EFI), a standard for replacing the BIOS. "Let's get together and replace 8-bit spaghetti code," is how Pat Gelsinger, Intel's chief technical officer, described the effort. Tiano is Intel's first EFI product.
Other chips on tap
Tanglewood will be one of a number of product announcements at the three-day conference, which runs from Sept. 16 to 18. Intel will also provide further details of "Prescott," the next version of Pentium 4, and "Dothan," a new version of the Pentium M for notebooks.
Both chips will begin to ship this year, Gelsinger said.
"We are going to...have '03 product and revenue shipments," Gelsinger said.
Both chips will be made on the 90-nanometer manufacturing process, which means that the average feature size of the chips will measure 90 nanometers (a nanometer is a billionth of a meter). Overall, this means the chips will be smaller and, over time, less expensive to make.
Many analysts and chip executives have said the shift to the 90-nanometer process will likely prove difficult for many companies and even prompt product delays because of the complexities involved.
"There are something like 1,600 or 1,700 process steps involved in making a 90-nanometer wafer," Gelsinger said. "It is stunning, the complexity."
Both Dothan and Prescott, for instance, will also use strained silicon, which involves adding an additional lattice of germanium and silicon atoms into the base layer of a wafer that helps electrons move more freely.
Intel's apparent success with 90-nanometer manufacturing could give it an advantage over competitors like AMD, which won't shift to 90-nanometer for a few months.
At the show, Intel will also discuss:
• Content services and content protection strategies for home networks. Last year at the fall conference, Intel introduced the media adapter, which lets home users hook TVs, stereos and PCs into a network. Now that adapters are hitting shelves, the company is trying to line up deals with content providers so that consumers can swap files legally.
Gelsinger indicated that the content deals to be announced at the conference won't revolve around trading protected video or music but around trading photos or piping Internet radio around the house. Still, the company will make announcements about content protection that could lead to the swapping of "high value" content, he said.
Along with this, Intel will also provide updates on reference designs for TV set-top boxes that are based on its silicon.
• A new chipset for notebooks that cuts down on energy consumption. The Pentium M, found in Centrino notebooks, uses much less energy than does the Pentium 4 by better controlling transistors. The new chipset, a group of chips that perform input-output functions, will essentially perform the same tasks.
• Wi-Fi chips for handhelds. In March, the company came out with its first Wi-Fi package for notebooks and is now bringing a similar product to handhelds, which will allow the handhelds to be used as phones. Intel will also disclose technical information on new Xscale microprocessors.
• Progress on integrating radios into processors. Currently, radio transmitters for technologies such as Wi-Fi and Bluetooth come on separate chips. Intel will provide updates on progress to integrate these components into other chips, which will make the radios virtually free. These radios will also be able to automatically reconfigure themselves to adapt to different frequencies.