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Intel shrinks chips to 90 nanometers

The chipmaker says it has produced memory chips in its labs containing 330 million transistors through manufacturing technology that will hit the mainstream next year.

Michael Kanellos Staff Writer, CNET News.com
Michael Kanellos is editor at large at CNET News.com, where he covers hardware, research and development, start-ups and the tech industry overseas.
Michael Kanellos
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Intel announced that its labs have produced memory chips that contain 330 million transistors, through manufacturing technology that will hit the mainstream next year.

The experimental SRAM (static RAM) chips measure approximately 109 square millimeters and contain up to 52 million bits of data, making them the densest SRAM chips ever produced, according to the company.

More importantly, the chips show that Intel is still comfortably meeting Moore's Law, as they were made using the 90-nanometer manufacturing process. Under Moore's Law, the number of transistors on a given chip doubles every 18 to 24 months, mostly because engineers find ways to shrink the size of the transistors.

Currently, the fastest chips are made on the 130-nanometer process, which means that circuits inside the chip measure around 130 nanometers wide. By shrinking the average feature size to 90 nanometers, Intel can cut the size of the processors in half or, more likely, add more features to its chips because it will be able to put twice the number of transistors in the same area.

The 130-nanometer chips began to arrive commercially in the middle of 2001; 90-nanometer chips are expected to hit shelves next summer. Proof-of-concept chips generally come out a year or so before actual commercial production.

The circuit designs used on the experimental SRAM chips will be used inside future processor caches, or pools of memory located near the processor, said Mark Bohr, an Intel fellow in the Technology Manufacturing Group.

"This is not just a test vehicle," he said.

Cache size has increasingly become an issue in recent years. McKinley, Intel's upcoming server processor, covers 464 square milimeters, making it one of the largest chips in years. A substantial portion of the chip, though, is taken up by the three caches, which sport more than 3MB of memory. Madison, its successor, will come with 6MB of memory.

Prescott, the code name of the next version of the Pentium 4, will be Intel's first 90-nanometer chip, Bohr said, although the technology will be adopted on other product lines.

Performance will also improve. The transistor gate, which determines whether a transistor is "on" or "off," measures less than 50 nanometers on 90-nanometer chips, smaller than the 70-nanometer gate length on 130-nanometer chips.

"The smaller the gate length is, the faster your transistors can switch on and off," said Bohr.