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Intel details Merced

The chip giant provides concrete details of Merced for the first time and announces a low-cost 64-bit chip architecture.

Intel provided concrete details of its 64-bit Merced processor for the first time at the Microprocessor Forum yesterday and announced a low-cost 64-bit chip architecture.

Providing particulars that are esoteric but essential for moving Intel to a 64-bit future, Merced targets high-end computer markets that Intel can only dream of now. The chip is due out in mid-2000.

Interestingly, Merced will come in a cartridge that is similar to the current Pentium II cosmetically but slightly smaller, according to a presentation given by Stephen L. Smith, a vice president at the Microprocessor Products Group.

Merced diagram

Under the hood, however, it's a completely different beast. In addition to having a new instruction set--which has been already outlined in some detail last year and earlier this year--the chip will use an entirely new cache memory architecture.

Cache memory is now taking up more and more real estate on processors and, in many cases, dwarfs the number of transistors found in the processor itself. For example, while a processor can consume between 5 million and 10 million transistors, a large cache memory can use well over 50 million.

The upshot is that this is emblematic of the crucial role this memory silicon plays in boosting the speeds of the most complex chips.

The Merced will have a "three-level cache hierarchy," compared to the two levels of cache used in the Pentium II chip. This will comprise a level-0 cache, a large level-1 cache, and a larger level-2 cache on the chip, delivering much higher levels of performance compared to the cache memory architectures used on Intel's current 32-bit chips.

Merced also will have a completely ravamped floating point unit. A processor is made up of a number of discrete computing units, which together constitute the whole processor. The floating point is one of the most critical and is used extensively in number-crunching for high-end scientific, engineering, and multimedia applications.

The new floating point unit will deliver 20 times the 3D graphics performance of a Pentium Pro's floating point processor and be three times faster than the one in a future 32-bit chip code-named Tanner, according to Smith.

Intel also mentioned that it is planning a chip dubbed "Deerfield" that will be its first 64-bit design targeted for lower-cost computers.

Merced on track
Smith was also quick to point out that Intel was on track for Merced, speaking to widespread concern about development delays. "Merced is well under way right now...we?re in final stages of validating, he said. "We're running an operating system on a [Merced test platform]."

He also added that Intel is "ramping final circuit layout" as well as "shipping silicon development vehicles," and that there "a large number of application porting centers," referring to the facilities that will allow software developers to write applications for the 64-bit Merced chip.

But other industry sources aren't so sure if Intel can meet the current schedule, claiming that compiler technologies still offer significant challenges and that a mid-2000 timetable may be too optimistic. A compiler is a program that prepares computer code so that it can be executed on a processor--and is vital for developing software for a new chip architecture like Merced.

Nevertheless, most large server vendors have committed to building systems around the chip, according to Linley Gwennap, vice president of MicroDesign Resources.

"[The Intel 64-bit architecture] is going to dominate the market," he said, "It is very likely that Intel will achieve a 50 to 60 percent market share within a couple of years."

In addition to PC companies such as Compaq and Dell Computer, vendors such as Silicon Graphics and Hewlett-Packard have said they will convert to IA-64 in the future, abandoning proprietary in-house architectures, Gwennap said.

McKinley in 2001
Smith reiterated that the McKinley processor, which follows Merced, has a target speed of 1 GHz (1000 MHz) and will achieve twice the performance of Merced.

By 2001, the company will release McKinley. McKinley will be followed by Madison in around 2002. Madison will likely be based around a copper interconnect scheme as Intel shifts to copper and away from the traditional aluminum connection technologies.

Intel will also manufacture chipsets (companion chips) for Merced-class servers, said Smith. Third parties will get licenses to make Merced chipsets. Licensees, however, won't likely shoot for widespread sales, but instead will serve niche markets.

These third parties will be supplying products "beyond the needs that we can supply," said Smith. So far, chipset licensees include HP, Unisys, and SGI. HP has said it will use its Merced chipset, which also works with HP's RISC processors, in its own servers.

Deerfield follows next. Deerfield will be Intel's first 64-bit chip that will be designed with cost-consciousness in mind. Deerfield will go into mid-range servers and workstations.

Deerfield will likely come out in the 2003 time frame.

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