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IBM combo technique tweaks transistors

Researchers at Big Blue manage to combine strained silicon and a silicon insulator in the same wafer, a new approach that could lead to faster, more efficient chips in a few years.

Researchers at IBM have come up with a new approach to building transistors that could lead to faster, more energy efficient chips in a few years.

Big Blue has managed to combine both strained silicon and a silicon insulator into the same wafer. Strained silicon improves electron mobility, or the speed at which electrons can travel through silicon. Silicon insulators reduce leakage, or the amount of energy inadvertently dissipated, a major problem facing chip designers today. The combination design, which will begin to appear in chips later this year, can improve transistor performance by as much as 20 percent to 30 percent.

"Both approaches have their merit, and they are complementary," said Nathan Brookwood, an analyst at Insight 64.

Since the beginning of the decade, chip designers have had to rethink many of the basic assumptions of their craft because of a growing conflict between power consumption and performance. Chips now on the market can contain as many as 250 million transistors, and the number is increasing because of Moore's Law. Not only is it extremely difficult to get power rapidly to this huge mass of transistors, the electricity required to run these processors generates problematic amounts of heat.

Small transistors are also prone to leakage. Some structures inside cutting-edge transistors are only a few atoms thick. To get around some of these problems, researchers have proposed replacing some silicon components inside chips with metal or creating transistors with two or three gates.

Silicon on insulator, a technique pioneered by IBM, was one of the first technologies developed to contain the energy problem. The technology can be found in the Opteron processor from Advanced Micro Devices.

Strained silicon will appear later this year in the Prescott and Dothan chips from Intel. The concept, which involves embedding a layer of silicon and large germanium atoms deep into the wafer to spread out pure silicon layers above it--was initially introduced in the late 1980s and early 1990s, but most dismissed it.

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"In '85, '86 or '87 if you proposed this, people would die laughing," Bernard Meyerson, chief technology officer at IBM's Technology group, said in an interview last year.

Although attractive in concept, inserting strained silicon is complex. Intel's new strained silicon chips, the company's first on the 90-nanometer manufacturing process, go through approximately 1,600 to 1,700 processing steps, said Pat Gelsinger, the company's CTO.

Although the marriage of strained silicon and insulating layers was to some degree inevitable, IBM asserts that it wasn't easy to accomplish. First, a layer of silicon germanium is deposited on the wafer, which is then topped with a layer of strained silicon and the insulating layer.

The wafer then gets flipped over, and the silicon germanium layer, which can create manufacturing difficulties and interfere with the insulating later, is evaporated. Transistors are then built on top of the exposed strained silicon layer, which is now on top of (rather than beneath) the insulating layer. IBM did not announce product plans, but a representative indicated that either technology could possibly be implemented in a few years.

IBM is announcing the laboratory breakthroughs this week and will make a more formal, complete presentation of its findings at the International Electron Devices Meeting in Washington, D.C., in December.

Additionally, the company has said it can incorporate the two main types of transistors--positively charged field effect transistors (PFETs), which carry positive charges, and negatively charged FETs (NFETs) for negative charges--into a single wafer inside a layer. Currently, NFETs and PFETs are inserted on separate layers. The technique can drastically improve performance, IBM theorized.