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Fujitsu plans four-core Sparc chip for 2008

The Sparc64 VI+ processor will have clock speeds of at least 2.7GHz, the company says.

Stephen Shankland principal writer
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Stephen Shankland
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SAN JOSE, Calif.--Fujitsu's Sparc64 VI+ processor, code-named Jupiter and due for release in 2008, is a four-core processor with clock speeds of at least 2.7GHz, the company said here Tuesday.

The chip will be built with a Fujitsu manufacturing process that permits features as small as 65 nanometers, or billionths of a meter, Takumi Maruyama, Fujitsu's manager of enterprise server development, said in a speech at the Fall Processor Forum. Even so, it will be relatively large; about 460 square millimeters in surface area.

Fujitu's Sparc64 family is a respected processor family, with good performance and reliability features drawn from the company's mainframe experience, but it hasn't been widely used outside Fujitsu's core market in Japan. That changed in 2004, when Fujitsu formed a partnership with Sun Microsystems. Sun scrapped its own UltraSparc V and moved to a jointly designed server line, called Advanced Processor Line, or APL, that uses Fujitsu's Sparc64 chips.

Sun, Fujitsu, IBM and Intel are racing to squeeze as much performance as possible out of their high-end server processors. The APL partnership starts in late 2006 with Fujitsu's Sparc64 VI, a dual-core processor code-named Olympus.

"The next-generation product, Olympus, has been taped out, and we have the chip working already," Maruyama said. Taping out a chip means that its design is complete and has been sent to manufacturing.

However, the processor is arriving a full year later than earlier expected. Two years ago, at the same conference, Maruyama said Olympus was due in the second half of 2005.

Sparc64 VI and VI+ use the same data pathway, called a bus, to connect to the rest of the system, meaning that the newer chip will plug into the older systems. "There is enough memory bandwidth on the bus" to accommodate the four-core chip, Maruyama said.

The APL partnership will include servers built with Sparc64 VI+ as well as VI, said Marc Tremblay, chief chip architect at Sun.

As with the Sparc64 VI, each core of the VI+ can execute two simultaneous instruction sequences, called threads. One event that can cause the chip to switch from its first thread to its second is when the first runs into a "cache miss"--in other words, when the chip has to wait because high-speed cache memory doesn't have the information the chip needs and must retrieve it from slower main memory.

Fujitsu calls its threading technology VMT, or vertical multithreading. "You can gain as much as a 20 percent performance increase, thanks to VMT," Maruyama said.

The Sparc64 VI will be able to execute four threads, and the VI+ eight. The chip family's future direction will include both multicore and multithread directions, Maruyama said.

The 423-square-millimeter Sparc64VI will consume about 120 watts of power, he said. He didn't absolutely promise that the VI+ will consume the same amount--a requirement to be able to drop the new chip into older systems. But he did say, "Yeah, we think it'll be something like that."

Sun also has three major chip designs of its own in development, all of which place an emphasis on many cores and threads. "Niagara," due by early 2006, is an eight-core, 32-thread chip geared for network-oriented tasks such as hosting Web sites. Its forthcoming sequel, Niagara II, will add multiprocessor abilities and better hardware acceleration of some software functions.

Finally, the "Rock" family, due in 2008, will be a high-end chip designed to run multiple threads and run each one as fast as possible.