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Chipmakers outline 600-MHz plans

Super-fast silicon from Intel, AMD, IBM, HP, and Toshiba will be previewed at a major industry conference next month.

The latest in super-fast silicon from Intel, AMD, IBM, Hewlett-Packard, and Toshiba will be previewed at one of the industry's leading chip gatherings next month.

At the 1999 IEEE International Solid-State Circuits Conference next month, Intel will discuss a 600-MHz version of the upcoming Pentium III chip, while IBM will disclose a new breed of PowerPC chip based on a cutting-edge production technique and a 600-MHz processor for server computers. The three-day conference in San Francisco and San Jose starts on February 15.

Advanced Micro Devices, meanwhile, will take the technical wraps off the K7, due in the second half. The chip is expected to best the Pentium III in a number of crucial respects and could give AMD the performance lead, according to, among others, Microprocessor Report editor Keith Diefendorff.

Though descriptions of new technologies at this highly technical conference are often couched in terms seemingly comprehensible only to chip design engineers, it all boils down to more powerful chips.

Inside the discussions lay descriptions of how the next generation of silicon will drive increasingly sophisticated calculations for software applications, 3D graphics images, video, audio, and data storage and retrieval.

These ISSCC disclosures are important because, in a number of cases, the ideas revealed at the conference often hit the streets within 18 months--or sooner. Last year, for instance, Intel publicly showed a diagram of the Xeon chip for the first time, while IBM and Digital gave timetables for boosting processor speeds to 1-GHz.

IBM also used the show to provide some of the first technical details of its copper technology. And, rather than marketing people in shiny suits, the presentations are made by the top chip designers and silicon academics in the world.

Intel will outline its upcoming Pentium III--previously known by its code name of Katmai--which the company describes in an ISSCC summary as a microprocessor for graphics and video which "adds 67 instructions for data streaming" and runs at 600 MHz. This is the speed that this chip is expected to hit later this year. It will debut at 450- and 500-MHz, according to Intel. The summary also highlights other circuit improvements.

On the 17th, Intel will then follow up with a preview of the Pentium III in San Jose. Software vendors and computer makers will gather in the San Jose Convention Center to show off upcoming products based around the Pentium III, although the chip won't come out until later in the month.

IBM will discuss a 580-MHz PowerPC chip design based on silicon-on-insulator (SOI) technology. The PowerPC architecture is used in Apple Computer's Macintosh computer line as well as a variety of other devices. IBM's SOI process protects transistors with an oxidized layer of insulation, creating a "blanket" that reduces harmful electrical effects that sap energy and hinder performance.

Thin is in
The proffered design will be based on leading-edge 0.12-micron manufacturing process for making ultrasmall transistors. Today, the most advanced chips are typically made on a "fatter" 0.25 process. Generally, the smaller the process, the more powerful the chip becomes.

"Traditional methods of [chip manufacture] are hitting the proverbial wall. Moore's Law puts enormous pressure on chipmakers, which are investing madly to find ways around the current set of walls," according to Linley Gwennap, editorial director of the Microprocessor Report.

IBM will also elaborate on a 600-MHz chip design for its 390 series of powerful mainframe computers, which typically uses ten or more processors. Development of new CMOS processors for this line is beginning to pick up speed after IBM switched over from an older Bi-CMOS design. The 10-processor S/390 G5 Turbo server is also one IBM's best selling computers, IBM Chief Financial Officer Doug Maine said recently.

Motorola to preview 450-MHz PowerPC chip
Motorola will preview a 450-MHz PowerPC chip with a special set of computer instructions called AltiVec. The 10.5 million transistor chip would use copper circuit interconnects, a technology which IBM has pioneered. To date, chips have used aluminum for interconnects. Copper designs are eventually expected to yield much faster chips.

Currently, the fastest commercial PowerPC chip on the market runs at 400 MHz. Both IBM and Motorola offer the chips, although IBM has offered a copper-based version since September of 1998.

Motorola has taken over the legendary Somerset design center--previously a joint venture between IBM and Motorola. The upshot is that Motorola will lead the design and manufacture of the PowerPC processor for the Macintosh.

Additionally, Hewlett-Packard will discuss a 500-MHz version of its RISC processor. The chip contains a whopping 1.5 megabytes of on-chip cache memory for boosting chip performance. Toshiba, NEC, and Samsung will also present new memory chip and multimedia processor designs, among a host of other new technologies.

Other presentations include:

  • A 256 megabit flash memory chip for mass storage presented by Hitachi. Typically flash memory chip capacities have been too small and pricey for applications that might replace hard drive in some cases.

  • A one gigabit synchronous DRAM memory chip from Samsung. Having more than 15 times the capacity of DRAM chips on the market today, this would be built on an advanced 0.14 micron process.

    An offbeat session will be entitled "They Don't Make Engineers Like They Used To...?" Moderator Thomas Lee of Stanford University will discuss engineers and education. "Education of most engineers used to involve a strong hardware component. Slide rules reinforced a connection to physical reality by gently refusing to provide orders of magnitude. However, with the complexity of modern circuits, have come similarly complex simulation tools. Has [this phenomenon] really caused mindless simulation to displace creative thought?"

    Michael Kanellos contributed to this report.