For chip designers, the next decade is going to be one big wrestling match with the laws of physics and chemistry. Images: Chips of the future
In late 2007, semiconductor manufacturers plan to begin to produce chips made on the 45-nanometer process, the next step in the progress of Moore's Law. They will then follow up with 32-nanometer chips two years later.
Chips produced on these manufacturing lines will be faster, consume less energy, contain more transistors and be cheaper to make. Texas Instruments said its 45-nanometer chips for cell phones will consume 40 percent less power while increasing performance by 30 percent. Thus, consumers will be able to play games or watch TV without killing the battery.
But making those chips will also be difficult and force manufacturers to alter the fundamental materials and processes they use today. Mistakes could mean falling behind competitors for several quarters.
"There are several things that make this one (the 45-nanometer jump) a little tougher, but it's not the first time we've done it," said Peter Rickert, director of process technology at TI.
This week, scientists from major companies and universities will gather in Honolulu for the 2006 Symposium on VLSI Circuits sponsored by the Institute of Electrical and Electronics Engineers.
Intel at the conference plans to describe its trigate transistor. In a standard transistor, electrons flow from a source to a drain across a planar channel, called a gate. A trigate features three gates--two vertical ones and a horizontal one--and sort of resembles a box.
The trigate also will contain a layer of metal, a major change, as current gates use polysilicon. These transistors also contain an enhanced form of strained silicon. Overall, the trigate transistors can provide 35 percent better performance at the same power level as current 65-nanometer transistors, said Mike Mayberry, director of components research at Intel.
Although it has made prototype chips with trigates, trigates will not be part of Intel's 45-nanometer chip. "We think there is a significant opportunity for consideration in the 32- or 22-nanometer nodes," Mayberry said.
He would not comment on whether metal would replace polysilicon in Intel's 45-nanometer chips. Metal can replace polysilicon on planar transistors.
TI, meanwhile, will show off a 45-nanometer SRAM memory cell that occupies only 0.24 square micron, about 30 percent smaller than the test 45-nanometer SRAM cell shown off by others so far. (SRAM cells are often used to test out new manufacturing processes.)
TI achieved the small size because it has decided to adopt immersion lithography, which involves drawing circuit lines on chips while the silicon wafer is immersed. TI also has enhanced many other features of its manufacturing process.
By adopting immersion for commercial production now, TI is moving faster than its rivals. IBM is considering adopting its Nemo immersion system for 32-nanometer chips, coming out two or three years later. Intel plans to skip immersion in 45-nanometer chips, but may adopt it for 32 nanometers.
At 45 nanometers, wet lithography will let TI squeeze more transistors on a chip than if it opted for dry.
"We're primarily concerned with doubling the density, and when we looked at the analysis there was no way we could stay the course with dry," Rickert said. "It (immersion) is built into the design rules."
When manufacturers actually begin to ship 45-nanometer chips varies. Intel, which has been one of the most successful in putting out a new manufacturing process every two years a la Moore's Law, plans to start shipping 45-nanometer chips to manufacturers in late 2007. The company was one of the first to ship 65-nanometer chips in late 2005.
TI plans to deliver samples of 45-nanometer chips to manufacturers in late 2007 and begin production in 2008. The company will also alter its recipe for various chips, optimizing them for different combinations of performance, cost and power efficiency. The company plans to incorporate metallic gates for high-performance microprocessors made on its 45-nanometer process.
Also at the conference, Freescale Semiconductor, the Motorola chip spinoff, will show off a version of silicon-on-insulator that it said can cut power consumption by 30 percent. Freescale, however, has not said if it will include the technology in its 45-nanometer chips.
Advanced Micro Devices, meanwhile, plans to start manufacturing 45-nanometer chips by mid-2008. This represents an acceleration of the company's plans. AMD hasn't even started to ship 65-nanometer chips. If the company can hit its mid-2008 mark, it will close the lead in manufacturing that Intel now enjoys, company executives have said.
How long will Moore's Law--which dictates that the number of transistors on a chip will double every two years--continue? Skeptics say that it may stop after the 22-nanometer generation of chips starts coming out around 2012 or 2014. At that point, chipmakers will have to adopt new structures other than transistors to carry signals because it won't be economically feasible to keep shrinking transistors.
Many, however, say that new materials such as nanowires will keep transistors alive for several more years. Stacking transistors vertically, but not shrinking them, will also allow chipmakers to continue to get many of the benefits, such as higher performance and lower costs, that shrinking transistors accomplishes today.
In any event, by around 2021, transistors could be so small that electrons will drift through them.