Why Intel doesn't include a memory controller on its chips

Tech Culture

If you want to know why Intel doesn't include a memory controller on its chips, you've got at a lot of factors, according to Intel CEO Paul Otellini.

A memory controller is a small piece of silicon that shuttles data between the processor and memory. Integrating it into the same piece of silicon, like on the Athlon from Advanced Micro Devices, improves performance. Integration essentially cuts down the commute time for electrons.

Intel does not integrate the memory controller. One reason is that memory standards change. Current Athlon computers, for instance, don't come with DDR II memory because the integrated memory controller connects to DDR I. Intel once tried to come out with a chip, Timna, that had an integrated memory controller that hooked up to Rambus. The flop of Rambus in the market led to the untimely demise of the chip.

Another reason is that Intel puts a lot of cache on its chips, which cuts down the need for an integrated memory controller, he said in an interview at the Intel Developer Forum.

"The only thing better than having an integrated memory controller is having the memory on chip," he said.

Size is an issue too. Intel makes processors on its most advanced manufacturing lines. (The current ones pop out chips with average feature sizes of 65 nanometers). A manufacturer can only process a finite amount of silicon on its most advanced lines each year: you can't rush the process. Consequently, the smaller a company makes its chips, the more it can produce in a year and the more revenue it can ultimately achieve.

Memory controllers add space to the size of the chips. In turn, this cuts down the number you can make.

Instead, Intel makes its memory controllers on the next-to-best technology generation, where silicon real estate goes for less of a premium.

It's also not an easy concept to sell.

"Nobody buys a chip because it has an integrated memory controller or it doesn't," he said. "They buy it because of the overall performance of the platform."

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