Trying to put new zip into Moore's Law

Under this principle, named for the Intel co-founder Gordon Moore, the chip industry in the last four decades has doubled the number of transistors it crams onto a chip about every 18 months.

That's a big reason that chips are now in our offices, homes, cars and toys--and often implanted in our pets and occasionally in our own bodies. Chips are almost ubiquitous, and where they're not, they probably will be soon.

But keeping the heart of innovation beating is becoming ever harder and more expensive. Making chips is an improbable blend of farming, photography and baking: think of your standard 300mm silicon wafer as a field where mostly metallic substances are "grown" according to patterns put in place by photolithography, and then "baked" at extremely high temperatures.

This agri-photo-baking takes big money: It costs $3 billion to $5 billion to build a single semiconductor fabrication plant, or fab. In the near future, that figure is likely to rise to $12 billion, according to VLSI Research. In the boom-and-bust cycle of the chip industry, it has become harder and harder to get a return on fab investments.

The remarkable progression of Moore's Law, meanwhile, involves continually shrinking almost everything to do with the chips. Today, the transistors in a high-end chip are no wider than the nucleus of a smallish bacterium--that's far smaller than the smallest light wave.

Until now, as chips became smaller, they also became faster in about the same proportion. It's still true for transistors, but it's no longer true for the wires used to connect transistors--and that slows performance gains. Daniel Edelstein, a program manager and fellow at IBM Research, says, "We're running out of steam."

Edelstein is leading a team of researchers from inside and outside IBM in developing a new way to solve the problem: using "self assembling" nanotechnology to make better insulators, raising performance. In this case, self-assembly involves creating so-called airgaps, vacuums a few nanometers wide that keep the billions of tiny copper wires in a chip from touching one another, instead of putting down a layer of insulating material and trying to align it effectively at the nanoscale. It's more efficient, and it means that IBM won't need to spend $50 million on photolithographic equipment.

A few weeks ago, Edelstein took me on a tour of the fab in East Fishkill, N.Y., that will be the first to use the self-assembly technique. While the technique is not quite done being tested, John E. Kelly III, IBM's senior vice president for research, says that "there is no question in our minds this is going to work," and that IBM will move to it by 2009, first for an existing high-end processor or a next-generation chip, then across its fabs.

Kelly says Edelstein has a "unique" ability to solve problems and work across the company to commercialize new technologies. In the last decade, he has led two other important breakthroughs, most notably the use of copper for the wires inside chips, replacing aluminum.

Each time, Edelstein has done it by working with a small group of two or three scientists to explore out-of-the-mainstream approaches to problems. He also goes beyond research, getting to know the manufacturing team to help him understand what it takes to get a novel technique into IBM's existing manufacturing process. (Becoming acquainted with the team is no small feat at a plant like the one in East Fishkill, which was designed to resemble an integrated circuit, creating an erratic hall structure that still befuddles Edelstein, even though he generally visits it once a week.)

With the self-assembling nanotechnology, he also had to go beyond IBM's walls, in part because IBM in the 1990s decided for a number of reasons--including costs and the desire to help create a Ph.D. feeder program--to work with a public-private consortium to develop a modern research fab run by the College of Nanoscience and Electronics at the State University of New York at Albany. This fab features one-of-a-kind equipment, and it is where Edelstein's team developed its techniques before moving it to IBM's fab in East Fishkill.

Kelly says IBM is developing a number of ways to use self-assembly in other parts of the chipmaking process.

And other companies are also racing to adopt the techniques. Steve Jurvetson, a co-founder of the venture capital firm Draper Fisher Jurvetson, says self-assembling technology holds huge promise for all types of semiconductors. He says two start-ups that his firm has backed, ZettaCore, which is developing memory chips, and Konarka Technologies, which makes solar power technology, are close to reaching commercial production of their products, thanks in part to nanoscale self-assembly.

Richard Doherty, director of the engineering consultant group Envisioneering, says self-assembly techniques should also greatly reduce the number of defective chips, helping to give fabs better returns.

The techniques could lead to more dramatic advances. Alain E. Kaloyeros, professor of nanoelectronics at SUNY Albany, says self-assembling nanotechnology will make it possible to etch a computer onto a pair of glasses, or to create "nanobots" that can float in our bloodstreams, searching for cancerous cells that the bots will then eliminate.

For now, the technique will help keep Moore's Law pumping, and with it a huge amount of innovation.

Michael Fitzgerald writes about business, technology and culture. E-mail: mfitz@nytimes.com.