The chip shows several improvements over its predecessors, in part because of improvements at the Texas Instruments factory where the CPUs are built using copper wiring technology, Sun said. In addition, better system performance comes through an improved "compiler"--the software that translates programs into instructions the chip understands, beta software that will be final when the product ships.
The chip is produced in Dallas using a manufacturing process that can etch features as small as 150 nanometers (0.15 microns), the same process used for the current fastest model running at 900MHz. Both models incorporate "low-K dielectric" technology to reduce power consumption.
UltraSparc III, introduced more than a year ago, is the foundation of a new line of servers at the Palo Alto, Calif., company. Sun is relying on the UltraSparc III to fend off resurgent IBM with its Power chip design and Hewlett-Packard with its PA-RISC and Intel Itanium designs.
Sun also is working on a lower-priced version of the UltraSparc III, the IIIi "Jalapeno," for systems with one to four CPUs. That chip will be produced on TI's 130-nanometer process, Sun said.
The UltraSparc III has 29 million transistors, the electronic elements that form the basis of much of a chip's processing circuitry. The UltraSparc IIIi has 87 million transistors, most of the difference due to the addition of 1MB of high-speed cache memory on the chip.
Jalapeno can switch off unused sections to reduce power use, the company said. And it includes for the first time a feature Sun Labs has been developing: "asynchronous" data transfer paths that let different parts of the chip be governed by different clocks. As chips get larger, it's more difficult to maintain the current design practice of having the entire chip march in lockstep to the beat of a single drummer.
The chip is the first to include Sun's "Jbus" connection technology for chip-to-chip interactions on multiprocessor servers.
In the longer term, Sun is working on its UltraSparc V chip, a split-personality model that can behave like an IBM Power or Intel Itanium chip depending on what processing task it's assigned.