MIT team shows experimental chip
Appearing at a Stanford University symposium today, an MIT research team described a novel computer architecture and microprocessor implementation.
At the Hot Chips IX conference in Palo Alto, California, today, MIT researchers described the MAP (Multi-Arithmetic Logic Unit Processor) chip. Each MAP chip contains seven processing units, which are divided into three "clusters" that process data simultaneously.
The chips use a built-in "router," analgous to the device used in large computer networks at corporations, to "talk" to each other and make sure information is being processed as efficiently as possible by all processors simultaneously.
"Everything is hooked together at the same time, instead of making data move from point a to point b in a line," explains Jim Lockmiller, a spokesperson for Cadence (CDN). The company provided expertise and specialized Cadence software to help design the chip.
MIT expects to have a machine that will string together 16 of these MAP processors together in a highly parallel system-prototype machine by early 1998.