Intel strikes back with next-generation chips

Next month's Intel Developer Forum will include a thorough airing of the company's new design philosophies, said Mooly Eden, vice president and general manager of Intel's Mobile Platforms Group. The company plans to brief hardware developers, partners, and analysts on the nitty-gritty details of its new microarchitecture, which is set to replace Intel's blueprints for desktop, mobile and server processors.

"We believe we'll be able to open a major gap," with the new processors, Eden said. Eden led the design team that created the original Pentium M processor, which is credited as the inspiration for Intel's embrace of low-power design philosophies and the model for Merom and Conroe. Merom and Conroe are expected to launch for notebooks and desktops, respectively, in the second half of this year.

The awkwardly titled Next-Generation Micro-Architecture (let's call it NGMA) has yet to receive a catchy name like Netburst, the Pentium 4 architecture it is replacing. But Eden believes it will quickly grab the attention of PC vendors, chip reviewers and analysts who have anointed the AMD64 architecture as the current performance leader. Intel has already disclosed a few details about NGMA. It uses 14 pipeline stages instead of the 31 used by Intel's Pentium 4 processors. Information is processed through a processor's pipeline. The more stages in the pipeline, the less work each individual stage performs, requiring the chip to run very fast and therefore very hot. Intel has moved away from that design strategy in favor of smaller pipelines that do more work per stage, and can therefore run at slower clock speeds.

The microarchitecture also allows the processor to issue four instructions per clock, rather than three, as on Intel's current chips. It uses advanced branch prediction technology borrowed from the Pentium 4 designs. And chips built on that microarchitecture will also share the unified cache introduced with the Core Duo processor, Eden said.

Chips built with NGMA will use 4MB of cache memory, Eden said. Cache memory stores frequently used data right on the chip, where it can be accessed much more quickly than data stored in external memory. Unifying the caches on a dual-core processor improves performance by expanding the amount of cache each core can utilize, which will produce a huge improvement on single-threaded applications that only use a single core, he said.

The combination of all those architectural changes will allow Intel to outperform AMD's planned offerings for the second half of 2006 without having to resort to adopting AMD's integrated memory controller design, Eden said. "It will take at least a year and a half to two years to close such a gap."

Intel has been hesitant to embrace the integrated memory controller since the failure of its last attempt to use such a design. Integrating the memory controller allows that vital gateway between the CPU and the memory to run at the speed of the processor, whisking data into the processor at a high rate of speed. But it also forces the processor to be designed specifically for a certain type of memory, which doomed Intel's Timna processor when its integrated memory controller was designed for Rambus' short-lived RDRAM standard.

Instead, Intel will count on its microarchitectural improvements and a faster front-side bus to deliver the 20 percent improvement in performance over AMD's chips, based on standard benchmarks, Eden said.

AMD is not planning any major architectural changes to its processors this year, but it does plan to introduce support for DDR2 (double data rate 2) memory. That memory standard can reach faster speeds than the current DDR memory used by AMD's chips, which will improve the performance of AMD-based systems.

The Spring Intel Developer Forum kicks off March 7 at the Moscone Center in San Francisco.