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AMD explores triple-gate transistors

The chipmaker unveils an experimental transistor with three gates, in a continued effort to find ways to increase performance while conserving electricity.

Advanced Micro Devices on Thursday unveiled an experimental transistor with three gates, in a continued effort to find ways to increase performance while conserving electricity.

The transistor, which the company is discussing at the International Conference on Solid State Devices and Materials in Tokyo, is the latest in a series of transistors from chipmakers that feature novel but not yet fully tested design conventions that their designers hope will help them navigate the difficult times ahead.

Semiconductor makers are at a juncture where they can't increase the speed of their chips or make them smaller without also worrying about heat dissipation or the loss of excessive amounts of electricity through leakage. Hence, they are rethinking the basic construction of their products, including the architecture of the transistor--the on-off switch inside a chip.

"The competition demands that we do this," said Craig Sander, vice president of process technology development for AMD.

Although chips have steadily become more complex, the challenge has accelerated in the past few years, many industry observers say. A chart shown by Intel President Paul Otellini at the Intel Developer Forum this week shows that chipmakers have gone from using only about 15 elements on the periodic table to make chips in the 1980s to using nearly half the elements on it now. Some of the newer elements are radioactive, noted Peter Glaskowsky, editor in chief of the Microprocessor Report.

Intel first introduced the concept of a trigate transistor in June, but there are also a host of ideas floating around corporate and university labs.

Among the concepts being debated: replacing the traditional silicon gate, which regulates the flow of electricity, with ; adding insulating layers to wafers; and physically straining the silicon lattice to allow electrons to move more quickly through it. AMD is also looking at dual, fin-shaped transistors as an alternate to triple-gate versions.

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Each manufacturer is tackling the problem differently. Intel's Prescott chip, shipping to computer manufacturers later this year, will contain strained silicon, but Intel has yet to adopt silicon on insulator, which advocates say cuts down on leakage.

By contrast, AMD and IBM are already selling chips with a form of silicon on insulator, but won't likely adopt strained silicon until 2005 or later.

The transistor that AMD is discussing at the Tokyo conference could be used in production by 2007, Sander said.

The transistor contains a number of recipes out of the experimental cookbook. For instance, it contains a fully depleted silicon-on-insulator layer, an improvement over the current chips that contain partially depleted silicon on insulator. Fully depleted means that any loose electrical charges are eliminated.

Additionally, the transistor contains nickel silicide gates, rather than silicon gates. Metal gates conduct electricity better than does silicon, Sander said.

As an unexpected benefit, the metal gate also strains the silicon lattice, which increases electron mobility. The unanticipated benefit comes as a result of the interaction between the metallic and silicon structures, Sander said.