IDF Fall 2007, part 5-- Penryn Inside

Stephen Pawlowski and Ofri Wechsler describe Intel's next-generation processor code-named Penryn.

Peter Glaskowsky
Peter N. Glaskowsky is a computer architect in Silicon Valley and a technology analyst for the Envisioneering Group. He has designed chip- and board-level products in the defense and computer industries, managed design teams, and served as editor in chief of the industry newsletter "Microprocessor Report." He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure.
Peter Glaskowsky
2 min read

In a technical session following Pat Gelsinger's keynote, Intel Fellows Stephen Pawlowski and Ofri Wechsler described Penryn, the newest dual-core processor from Intel. Penryn is shipping to OEMs now, with a formal launch scheduled for November 12. The full details of Penryn are available elsewhere, so I'll just focus on some interesting points from the presentation.

Penryn has a "deep power-down" state called CC6 (I don't know what the acronym means). The state saves the core's architectural state into a special on-die memory. According to the presentation, the chip's lowest power consumption can only be achieved when both cores on the chip are in the CC6 state.

Penryn will also support "dynamic acceleration," in which one core of the chip can run faster if the other core is idle. Wechsler's slide showed "up to 7%-8% gain" but he verbally referred to "5% to 10% gains". Either way, that isn't very significant, but I suppose it's better than nothing.

There was also a slide showing how Penryn fits into Intel's processor roadmap for server, desktop, and mobile systems. Interestingly, the slide said that Penryn will be available at speeds in excess of 3 GHz for server and desktop systems, but this comment was notably absent for the notebook portion of the roadmap.

There was also some talk about Nehalem, a processor due out late next year, which introduces an AMD-like system architecture. Processors will have an on-die memory controller as well as one or more QuickPath interfaces that can connect to I/O devices or connect processors together in a multi-processor system.

QuickPath was designed primarily for 2- and 4-processor systems, but "can be extended further."

Also, the word was that QuickPath will be "not very prevalent" in mobile and handheld systems, possibly implying that it's relatively power-hungry. Certainly it wouldn't make much sense to force-fit a server-optimized system architecture into a notebook. We'll have to see how that goes.

Further details on Nehalem will have to wait until the next IDF in the spring of 2008.

There was also a press briefing on Penryn that followed this presentation, but it primarily served to rehash the information presented in the keynotes and the technical session. An Intel representative touted the inherent advantages of the Core microarchitecture, which forms the basis of today's Merom and Conroe processors as well as Penryn and Nehalem, over AMD chips by pointing out that the Core design can execute four instructions per clock cycle, whereas AMD's processors only execute three instructions per cycle. But in truth, this is not as substantial a difference as the numbers imply. In real-world software (and benchmarks) the number of instructions executed per cycle, on average, is usually only slightly more than one.

That's about it for today. I'll be back tomorrow with "Mobility" and "Ultra Mobility" keynotes plus more technical sessions.