In the next few years, advanced silicon chips might require an extra layer of germanium on top, according to UC Berkeley professor of electrical engineering Chenming Hu, speaking at an all-day research symposium held at the campus.
Chip designers right now are stuck in a dilemma. They need to make internal chip components like transistor gates thinner and smaller; reducing the size of those components, however, causes electrical leakage and other problems. To solve this problem, chip designers have concocted new materials and changed their circuit designs, but it's an ongoing problem.
By adding a three nanometer layer of germanium on silicon wafers, electron mobility would increase but not create negative side effects. The germanium layer could be added as follows: a germanium wafer with an embedded hydrogen layer could be stuck to a silicon wafer. The dual wafer could then be heated, which would force the hydrogen to expand and cleave off the unwanted germanium.
Yes, adding germanium would add costs, but the actual amount of material consumed would be somewhat low, he said. The industry as a whole only processes 2 square kilometers worth of silicon wafers a year.
Hu is a returnee at Berkeley. For the past couple of years, he has served as CTO at Taiwan's TSMC.