I'm blogging today from Hot Chips 19, the annual chip technology conference hosted by Stanford University. I'm planning to summarize each session as it happens.
Before the sessions began, there were some announcements--expected attendance, for example, is about 600 people.
Famed computer architect John Mashey spoke on behalf of the Computer History Museum, giving an update on museum exhibits and inviting Hot Chips attendees to visit while they're in town. The museum will have one of the two working copies of Charles Babbage's Difference Engine on show this fall, for example.
The first session is a collection of three papers about IBM's Power6 server processor. The Power6 is generally regarded as the world's most sophisticated microprocessor, and it's certainly one of the world's most expensive; a 16-processor system can cost well over $2 million. But you get a lot of advanced features for the money, and this session describes some of them.
The first paper is titled "Fault-Tolerant Design of the IBM Power6." The Power6 runs as fast as 4.7GHz, up to seven instructions at once, with two threads per core and two cores per chip. The chip has 790 million transistors.
This paper is about Power6's RAS (reliability, availability and serviceability) features. These features are critical to delivering the high level of reliability that customers require for mission-critical servers in industries such as banking, securities, telecommunications and transportation.
The Power6 can detect and repair errors in just about any part of the system, and disable units or I/O connections that can't be repaired. If something has to be disabled, the system can "fail over" to an alternate unit.
The second presentation is "System Performance Scaling of IBM Power6-Based Servers." It describes how Power6 chips can connect up to eight channels of DRAM, 32MB of L3 cache, and seven other processors within a single node of a multiprocessor server. Processors include inter-node connections as well, so a single system can comprise eight nodes (64 dual-core processors) without further "glue" logic. Now that's what I call a scalable system architecture...
The final presentation in this session is "The Third Generation of IBM's Elastic Interface on Power6." This talk describes the chip's many I/O channels in greater detail. The Power6 has 80GB/s of bandwidth to the L3 cache, 75GB/s to the DRAM, 80GB/s of intra-node links, 50GB/s for inter-node links, and 20GB/s of local I/O bandwidth for network and disk interfaces. (And who wouldn't like to have 20GB/s of network and disk bandwidth?) If you're counting, that all adds up to 305GB/s; IBM conservatively claims a total 300GB/s.
I'll be back soon with a summary of the first conference keynote, from Vernor Vinge...