Citing, has for the time being ceased development of an electronics package called a chipset that's at the heart of Big Blue's Itanium servers.
, Big Blue has been developing its family of Enterprise X Architecture chipsets, vital components that connect central processors to memory and other parts of a computer. These chipsets could be used either with Intel's Xeon family of processors or with the chipmaker's higher-end but less widely used Itanium 2 models.
In a shift from its predecessors, the new generation of IBM's Enterprise X Architecture chipset family doesn't support Intel's Itanium chip.
Big Blue's step away from Itanium is further evidence that customers generally prefer Intel's Xeon family, especially since it now includes 64-bit extensions that previously were a major Itanium advantage.
"We did forgo (Itanium support) on X3. It is a function of the market acceptance of Itanium," Bradicich said in an interview Tuesday. However, Itanium support could be reinstated with a successor called X4 if there is demand, he added.
It's not a surprise that IBM isn't the strongest Itanium supporter, given its promotion of its own Power processors--one of the top two major RISC, or reduced instruction set computing, chip designs at which Intel is aiming Itanium. Even so, IBM's step away from Itanium is further evidence that customers generally prefer the Xeon family, especially since it now includes 64-bit extensions that previously were a major Itanium advantage.
"The migration strategy Intel once imagined--which was at the point where Xeon users started knocking up against the limited headroom of Xeon...(and) would naturally want to migrate to Itanium--has largely been blown apart by the 64-bit extensions capability of (Advanced Micro Devices') Opteron and now 64-bit Xeon," said Pund-IT analyst Charles King.
Intel sees things differently, pointing out that 40 of the world's 100 largest companies use Itanium servers. "There is significant opportunity for Itanium in the $21 billion market for RISC replacement, mainframe migration and high-performance computing," said spokeswoman Erica Fields.
And several others besides Intel have their own Itanium chipsets: Silicon Graphics, NEC, Fujitsu, Hitachi, Unisys and Itanium co-developer Hewlett-Packard.
The second generation of IBM's EXA chipset family links as many as 16 Itanium 2 processors in, introduced in 2003, and as many as 32 Xeon processors in the x445.
The new X3 chipset will be used in conjunction with Intel'sversions of Xeon. Another chipset, called X4, is in development and is scheduled to arrive roughly 18 months from now with the next generation of Xeon chips, Bradicich said.
With X3, code-named Hurricane, IBM combined several previously separate chips into one, Bradicich said. Preceding chipsets had an easier time dealing with either Itanium or Xeon processors because a separate chip was used for the processor interface, but with X3, IBM integrated that interface into the main part of the chipset. That integration makes the chipset cheaper but also would have made Itanium support more expensive.
The X3 chipset is used in IBM's four-processor x336 server, due to go on sale within 90 days, but X3 also will see use on higher-end multiprocessor systems, Bradicich said.
"We have a lot of flexibility. We built this X3 Hurricane chip to scale for four, eight, 16 or 32 processors, plus it will accommodate dual-core in each of those configurations," he said. IBM spent more than $100 million over three years developing X3, he added.
Dual-core processors combine two processing engines onto a single slice of silicon. Adding support for 32 dual-core processors led Bradicich last year to say that X3 would enable. Since then, however, naming conventions have changed, and a dual-core chip is considered a single processor.
Hurricane includes two major components, controllers for the computer's memory subsystem and a "scalability port" that is used to link four-processor groups together. With Hurricane's predecessor, the "Cyclone" memory controller and "Twister" scalability port controller were separate chips, Bradicich said.
The memory controller was once linked to a large pool of high-speed external memory called a cache, but X3's access speeds are fast enough that the cache no longer is needed. The technology for addressing the cache memory remains in the chipset, though, as a way to speed access to needed data, he said.
With X3, one component, code-named Calgary, is still separate. It links Hurricane to the input-output subsystem, which lets a computer use thecompared with the PCI-X of the X3's predecessor. A new version of Calgary coming by the end of the year will build support for a newer input-output system called .
X3 also continues support for hardware partitioning technology that lets each four-processor unit house a separate operating system, Bradicich said.
The communication channel that links the processor to the chipset is called the front-side bus. X3, like Intel's chipsets, uses a 667MHz front-side bus that's substantially faster than the 400MHz bus on current Xeons geared for four-processor machines. And like Intel's chipset, X3 also employs dual front-side buses for each chip, a move that makes it easier to accommodate the communication demands of future dual-core models, Bradicich said.