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Sun says UltraSparc V two chips in one

The company has only just started delivering its UltraSparc III processor, but already it has begun touting the split-personality features of its upcoming UltraSparc V chip.

Sun Microsystems has only just started delivering its UltraSparc III processor, but already the company is touting the split-personality of its upcoming UltraSparc V chip.

The UltraSparc V will be able to switch between two different modes depending on the type of work the computer is doing, said David Yen, general manager of Sun's processor group. One mode will be good for heavy-duty calculations, the other for business transactions such as recording or retrieving information in a database.

"We'll have architecture that will explore instruction-level parallelism, like the Intel Itanium, and we will also explore thread-level parallelism, like the IBM Power4," he said. "But instead of having two separate chips, we'll design the chip so we have the ability to switch through software to support either of the workloads."

With instruction-level parallelism, a chip sorts different types of instructions into several parallel "pipelines" that do their work simultaneously, explained Insight 64 analyst Nathan Brookwood. With the newer concept of thread-level parallelism, or symmetrical multithreading, several different computing tasks can work their way through a single pipeline at the same time.

But adding both these features to UltraSparc V requires a major overhaul, Brookwood said, and competitors Intel and IBM likely will have achieved the same thing by the time UltraSparc V arrives.

"To the extent they go and do instruction-level parallelism and symmetrical multithreading in one fell swoop, that's a lot to bite off," Brookwood said. "There are some technical folks who would say it's better to do one big piece of technology at a time."

The holdout
The success of the UltraSparc line is key for Sun, the only major server manufacturer to resist the pressure to use Intel chips. Much of Sun's influence comes from the widespread number of programs designed to run on its Solaris operating system atop UltraSparc chips. Switching to another chip would be disruptive to software companies such as SAP or Oracle.

Indeed, what has separated Sun from competitors such as Compaq Computer in recent years has been the support of software makers, said Sanford Bernstein analyst Toni Sacconaghi. "Sun had the worst microprocessor performance by almost any benchmark when it gained the most share," he said. "By contrast, (Compaq's) Alpha had the best and really didn't do anything."

Designing its own chips is very expensive for Sun. The advantage, though, is that customers' old software will work on the new chips, making upgrades easier.

Sun began shipping the UltraSparc III chip running at 750 MHz in late 1999. Sun and Texas Instruments, which manufactures the UltraSparc line, recently announced a new version of the UltraSparc III running at 900MHz and using faster copper interconnection technology.

Sun originally planned a 900MHz UltraSparc III using the slower aluminum interconnects, but with the copper version done that chip won't be produced, Yen said. The copper version will begin shipping within 90 days.

UltraSparc IV, a relatively small change from UltraSparc III, will arrive "at frequencies much higher than 1GHz," Yen said. UltraSparc V will run faster than 1.5 GHz.

Intel in May debuted the Itanium processor, its high-end answer to UltraSparc and IBM's Power chip line. Shortly after, Compaq abandoned its own highly regarded Alpha-chip line, handing Intel the chip's design staff--including their experience with symmetrical multithreading.

Hewlett-Packard co-developed the Itanium with Intel and is in the midst of a years-long transition to it from its own PA-RISC chips. SGI is likewise moving from MIPS chips to Itanium. IBM, while supporting Itanium, also has its own Power processor line.

These high-end chips all are 64-bit designs, which means they bite off chunks of data and instructions 64 bits at a time and can accommodate vast amounts of memory. Intel's current 32-bit chips--Pentium, Celeron and Xeon--can generally only access much smaller amounts of memory, making them ill-suited to high-end computer tasks such as dealing with vast databases.

Size a factor?
The dual-personality approach will give the UltraSparc V relatively large dimensions, but because much of the chip will be used in either mode, the size penalty probably won't be severe, said Mercury Research analyst Dean McCarron. Chip size is critical because it has a direct bearing on how much it costs to make a chip, how much power the chip consumes and how much heat it gives off.

Because Sun plans to use software to figure out which mode the chip operates in, "you wouldn't necessarily have to have a duplication of hardware," McCarron said. "Basically you're just deciding how best to allocate the execution units of the processor among the instruction streams coming in."

Sun is playing catch-up in some ways. The current Pentium CPUs as well as AMD's Athlon and IBM's Power chips all can accomplish a task called "out-of-order execution," in which a chip isn't confined to executing instructions in the order the software sends them, Brookwood said.

Out-of-order execution, a prerequisite for Sun's goal of instruction-level parallelism, lets a chip work on a new instruction even if the first is hung up in the chip waiting for data from slower parts of memory, Brookwood said.

IBM in particular has pushed the concept forward with its Power chips, Brookwood said. "There's an awful lot of parallelism going on in Power4," he said, noting the two CPUs etched on the same piece of silicon, the symmetrical multithreading and the out-of-order execution abilities. "That'll be the chip to beat when it shows up at the end of the year."

Though adding instruction-level parallelism to a chip improves its performance without requiring software companies to rewrite their programs, there is a hitch, Brookwood said. The problem relates to compiler software--which translates programs humans have written into instructions a chip can understand. Compilers are key to making sure the instructions fed to a processor are optimized to take advantage of the chip's features.

"Instruction-level parallelism is very compiler-sensitive," Brookwood said. It's a lesson Intel is learning with the Itanium.

Though the 900MHz UltraSparc III chips will arrive first in workstations, the chip will be used in servers "very closely" afterward, Sun's Yen said--certainly by the end of the year.

It's likely the 900Mhz UltraSparc chips will arrive on the coming "StarCat" high-end server from Sun, which can handle more than 100 CPUs in some configurations. "We like to have some kind of a wow effect," Yen said.