New standard to speed chip connections

A key industry group is aiming to come out with a new specification for a high-speed chip connection technology that could more than triple the bandwidth for data.

Michael Kanellos Staff Writer, CNET News.com
Michael Kanellos is editor at large at CNET News.com, where he covers hardware, research and development, start-ups and the tech industry overseas.
Michael Kanellos
3 min read
SAN JOSE, Calif.--A key industry group is aiming to come out with a new specification for a high-speed chip connection technology that could more than triple the bandwidth for data.

The HyperTransport Consortium, which controls the specifications for the chip-to-chip connection technology behind Advanced Micro Devices' upcoming Opteron processor, expects to release the new specification, HyperTransport 2.0, a year from now. HyperTransport is an effort initiated by AMD to define a new high-speed technology for connecting PC components.

HyperTransport 2.0 will provide data transfers between chips at 20 gigabytes to 40 gigabytes per second, depending on the system architecture. Such speeds will greatly increase the performance and versatility of servers or desktops, said Gabriele Sartori, president of the consortium and director of strategic alliances at AMD.

"When you have the bandwidth available, you find a way to use it" for beefing up servers or enabling better 3D, Sartori said during an interview at the Platform Conference here.

HyperTransport 1.0 features an aggregate data transfer rate of 6.4 gigabytes to 12.8 gigabytes, depending on the configuration.

The group also came out with an improved version of the 1.0 specification this week, HyperTransport 1.05, and kicked off a compatibility program aimed at making it easier for other companies to make HyperTransport-compatible products.

HyperTransport, an idea that partly originated out of technology from defunct computing giant Digital Equipment, is one of the primary features of AMD's upcoming Opteron and Athlon 64 chips, which are expected to help AMD move from the fringes of the corporate market toward the mainstream.

The technology essentially improves performance by eliminating many of the bottlenecks in existing servers. In most servers today, the processors and memory trade data over a central system bus, similar to a bridge or freeway that connects the suburbs to a central business district. Designing a chipset for an eight-processor server is often fraught with difficulties and delays because of the complexities in designing an efficient bus.

In HyperTransport servers, the central bus is eliminated. Instead, processors and memory are spread out and united by a high-speed ring road, similar to the decentralized live-work areas that have become common in high-population areas. Memory latency, or the time gap between when a processor requests data and when it actually retrieves it from memory, are reduced, according to AMD executives and various analysts.

Another benefit comes in reduced design costs. A two-processor server can be largely constructed out of the same parts needed to build a four- or eight-processor one, a stark contrast to traditional servers. One Taiwanese manufacturer is tinkering with a server that easily can be switched from two to four chips by snapping in an extra board, Santori said. "It is being commoditized very well," he said. "There are no more exotic chipsets."

The 2.0 specification will come out late this year or early next year, he added. The 2.0 version will provide 3 gigabits to 5 gigabits per second for each pair of pins, the electrical contacts that physically transfer data. Assuming a rate of 5 gigabits per second, a 16-bit HyperTransport link--incorporated onto a microprocessor or other chip--would provide data transfer rates of 20 gigabytes per second, while a 32-bit link will switch data at 40 gigabytes. Current HyperTransport links exchange data at 1,600mbps per pin pair, topping out at 12.8 gigabytes for 32-bit devices.

The new 1.05 specification improved various features of the existing specification, including error correction.

More speed for HyperTransport may come in the future through the addition of optical technology, said Brian Wong, vice president of communications products at Primarion. Primarion, which develops chip-to-chip connections based on optical fiber, hopes to release a proposal for an optical version of HyperTransport later this year. Optical fibers communicate through photons, which are faster than electrons and generate less heat.

Thirty-nine HyperTransport-compatible products have already reached the market. Although Cisco Systems, Nvidia, Apple Computer and others have joined the HyperTransport Consortium, AMD will likely be the biggest user of the technology, Sartori said. Still, that should give the specification enough support to survive, said Jim Turley, a microprocessor analyst and editor of JimTurley.com. Most of AMD's processors for the foreseeable future, after all, are based around it.

"They've achieved critical mass," Turley said.