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Intel peels back the layers of Core

The company's new chip design tries to get all its work done in the shortest possible amount of time, using the least possible energy.

Intel is using fusion in its upcoming chips. But don't worry--you won't need to be a nuclear technician to use "Merom" or "Conroe" chips.

The company's new Core microarchitecture takes advantage of similarities to fuse certain types of x86 instructions into more manageable chunks, executives said Wednesday at the Intel Developer Forum.

Intel's strategy was, at one point, to emphasize frequency improvements as the driving force behind better performance, said Steve Pawlowski, an Intel senior fellow and chief technology officer in the company's Digital Enterprise Group.

IDF Spring 2006

But those days will soon come to an end with the introduction of three new chips--code-named Merom, Conroe and Woodcrest--based on the Core microarchitecture. Merom is a notebook chip, Conroe is slated for desktops, and Woodcrest is for servers. Intel has said all three will deliver significant performance increases compared with current chips--as much as an 80 percent improvement in the case of Woodcrest--while consuming less power.

One of the ways that the new architecture makes this happen is through macro-ops fusion and micro-ops fusion, said Ofri Wechsler, an Intel fellow and director of the company's mobility microprocessor architecture. For some time, Intel's chips have been breaking down instructions into smaller, more digestible pieces as they move through the chip. When Banias--the Pentium M chip that is the model for the Core architecture--was introduced in 2003, it used a technique called micro-ops fusion to glue pieces taken from the same instruction back together. This reduced the overall amount of work the processor needed to do to complete a task.

With the Core microarchitecture, Intel's chips can piece together more of these micro-ops, Wechsler said. But the new chips will also be able to combine separate large instructions that usually appear in pairs into a single instruction. This is known as macro-ops fusion. This increases performance, but also reduces the amount of power used by the chip, since it doesn't have to work as hard to get the same amount of work done, he said.

Pawlowski and Wechsler also reviewed several aspects of the design of the Core chips, such as a shared cache and faster processing of multimedia instructions.

One design technique that doesn't appear imminent is an integrated memory controller, which is a prominent feature of Intel rival Advanced Micro Devices' chips. Pawlowski was on the team that almost 12 years ago designed the front-side bus architecture that Intel continues to use in its chips, he said.

A system's memory controller handles the interaction between the CPU and memory. In AMD's chips, that feature is built onto the chip where it can run at the same speed as the processor and quickly access data stored in memory. Intel's designs use a front-side bus, so the complexity of that transaction is handled outside the chip. This is slower, but more flexible, since Intel doesn't have to redesign its chips as memory standards change. And it's also cheaper, according to .

The improvements that Intel has built into the Core microarchitecture chips will ensure that Intel won't pay a penalty for the front-side bus in the short term, Pawlowski said. At the same time, extending the lifespan of that bus technology allows Intel to take advantage of a ton of accumulated knowledge within the company about the bus, he said.