The University of Texas plans to collaborate with Big Blue on building a processor capable of making more calculations per second than many of today's top supercomputers.
Researchers at the university conceived the TRIPS (Tera-op Reliable Intelligently adaptive Processing System) chip architecture. But a collaborative effort with IBM's Austin Research Lab will bring it to reality, according to IBM. The Defense Advanced Research Projects Agency (DARPA) is funding the effort with an $11.1 million grant.
At the heart of the TRIPS architecture is a new concept called "block-oriented execution," IBM said. Whereas most chips can handle just a few calculations at a time, a processor based on TRIPS architecture will be able to perform large blocks of them simultaneously, the company said.
A chip capable of performing 1 trillion operations, a tera-op, won't emerge from the project until 2010. However, researchers are readying a prototype chip with four processor cores--the computing units inside a processor--that is expected in less than three years.
These cores will be designed to churn 16 operations per clock cycle each, for a total of 64 operations per clock cycle. The prototype chip is expected to operate at 500MHz, which means its internal clock should complete 500 million cycles per second. That adds up to about 32 billion operations per second, theoretically.
TRIPS chips prototypes will be running in the lab by December 2005, IBM added.
By 2010, the research team expects to accelerate the chip's speed to 10GHz. It will be capable of performing 1 trillion operations, or calculations, per second, the Armonk, N.Y.-based company said.
The chip is part of an overall supercomputer design effort at IBM called PERCS (Productive, Easy-to-use, Reliable Computing System) that DARPA is also funding. In the PERCS program, IBM is trying to build a peta-op (one quadrillion operations per second) system that can analyze its own work flow and optimize its own hardware and software resources by 2010. Ultimately, IBM hopes to use technology the program develops in its commercial mainframes and servers.
Cray and Sun have received similar grants from DARPA for developing new supercomputer architectures. Sun is working on a 100,000-processor supercomputer that will include asynchronous chips, which means that chip circuits will not have to be synchronized. Reducing synchronization will drastically reduce energy consumption and the time required to develop the machine, said Jim Mitchell, who heads up Sun's labs.
IBM's Microelectronics division is also working on the project and will likely manufacture the chip.
Getting chips to perform more tasks simultaneously is the dominant aim of microprocessor designers. At the Hot Chips conference in Palo Alto, Calif., earlier this month, Sun Microsystems discussed plans to fuse two processor cores into a single chip.
For its part, IBM, which already sells the two-core Power4 chip, plans to bring multithreading to the Power5. Multithreading allows a single core to do two or more tasks simultaneously.
Intel already has embedded threading in many of its chips and plans to come out with a commercial dual-core chip in 2005.
The TRIPS project in many ways fits the strategic aims of both IBM and the University of Texas. Although it doesn't manufacture nearly as many chips as Intel, IBM is trying to increase its prominence in the semiconductor world through collaborative efforts and through licensing its technology to third parties. For its part, the University of Texas is aggressively building its graduate programs, particularly in engineering and sciences, sources said.