Hewlett-Packard unleashes a new version of its own PA-RISC chip line this week, one of at least four new generations HP will sell in coming years while it phases in new chips from Intel.
The company said the two-pronged chip strategy is required, because customers who buy high-end computers are reluctant to change chip architectures quickly, thus HP must extend existing chips for a certain period of time.
The PA-RISC 8600, due in powerful computers in the first quarter of 2000 at speeds of 550 MHz, is a close relative of the current 8500, said Doug Bartlett, R&D manager at the VLSI Technology Center at HP. "The 8600 was a relatively quick release," he said.
The update is one of several announcements made this week at the Microprocessor Forum, an annual chip confab in San Jose, California. Other companies, including IBM, AMD, Compaq Computer, and Sun Microsystems all plan their own chips that compete against Intel's high-end chips.
The 8600 uses the same core as the 8500, Bartlett said. And because the 8600 chip also uses the same surrounding electronics, it can be dropped into existing 8500 systems, he said. The 8500 was announced in March 1997 and introduced in October 1998.
One new feature, though, is that two 8600 chips can run in "lockstep"--in other words, to execute exactly the same instructions at the same time. That feature appeals to users of high-end server computers who need their machines to stay up and running all the time, even if critical components such as CPUs fail. HP is in the midst of a major effort to push its high-end systems to the level where they limit computer downtime to just five minutes a year.
The PA-RISC chips are part of a dual-pronged strategy to support both HP's own PA-RISC chips and Intel's upcoming high-end IA-64 chips. Those IA-64 chips actually were spawned at HP, which decided to call upon Intel for its mass manufacturing prowess so the chip wouldn't be relegated to niche status.
HP is developing the 8700, 8800, and 8900. New Unix servers from HP, such as the 8-CPU N-class and four-CPU L-class machines, though, can accommodate either the PA-RISC chips or the IA-64 chips.
Room for improvement
As they prepare future chips, companies are taking a variety of measures to keep their chips competitive. These include IBM's "chip multiprocessor" (CMP) technique of bunching multiple CPUs on a single chip and Compaq's technique of trying to reduce a chip's idle time by letting it do several independent tasks, called "threads," simultaneously.
"All of these solutions are viable answers," Bartlett said. "The debate is when it is a good time to decide to make one of these jumps."
Multi-CPU chips, for instance, typically result in larger chips, which means that fewer of them can be made per silicon wafer, Bartlett said. More importantly, the yield, or number of good chips per wafer, declines with multiprocessor chips. Both factors result in increased cost.
The multiprocessor solution will not likely have much of an effect until the advent of the 0.13-micron chip manufacturing process arrives, he said. That technology is about two generations away right now; companies such as Intel and AMD w have just begun moving to a 0.18 micron process.
HP is looking at innovations of its own, including integrating the memory controller--the part of a computer system that talks to the separate RAM chips--into the chip itself. Those duties currently are handled by separate chips.
HP did not disclose plans at the moment, but Bartlett said that architectural changes such as multicore processors and multithreading could be incorporated both HP's PA-RISC line and Intel's IA-64 processors. Intel has said its IA-64 plan is focusing initially on getting "better building blocks" before moving on to more refined technologies.
These proposals all relate to one of the recurring problems in computer architecture, stated Jim Davis, general manager of the IA-64 program at HP: "How do we connect the memory and CPU together better?"
The first 8600 samples have been produced, Bartlett said. The chip will connect to 133-MHz conventional SDRAM memory.
According to a recent HP chip road map, the 8700 is scheduled to debut at about the same time as Intel's second IA-64 chip, the "McKinley," which is due by the end of 2001. The 8700 is expected to run at a speed of 700 MHz.
The 8800 is scheduled to debut at 900 MHz near the time Intel's third-generation "Madison" and "Deerfield" IA-64 chips arrive. The 8900 is expected to run at a speed of 1.2 GHz, HP said.