1000-MHz chips on tap for Intel

The chipmaker's road map calls for improving its 32-bit architecture into the next century and reaching 1000 MHz.

Brooke Crothers Former CNET contributor
Brooke Crothers writes about mobile computer systems, including laptops, tablets, smartphones: how they define the computing experience and the hardware that makes them tick. He has served as an editor at large at CNET News and a contributing reporter to The New York Times' Bits and Technology sections. His interest in things small began when living in Tokyo in a very small apartment for a very long time.
Brooke Crothers
4 min read
SANTA CLARA, California--Intel detailed a road map for upcoming microprocessors that will extend variations of its current technology well into the next century and range up to 1000 MHz in speed.

Most prominently, technology code-named Foster will represent a new processor "microarchitecture," according to Fred Pollack, director of measurement, architecture, and planning and Intel's microprocessor products group.

Foster will be a 32-bit design, very similar to a chip design dubbed Willamette. Foster will be intended for high-end PC servers and Willamette targeted at desktops, Pollack said.

Foster chips could hit speeds of 1000 MHz or higher when they come out late in the year 2000 or early 2001. "This is our target," Pollack said. Currently, the fastest rating on Intel chips is 450 MHz.

The upshot is that Intel intends to continue upgrading its 32-bit chip lineup, which features the Pentium and Pentium II (including Xeon and Celeron) processors, as a kind of insurance against its upcoming 64-bit chips, which will be radically different, higher-end designs. Though potentially a quantum performance improvement over 32-bit technologies, Intel?s 64-bit Merced and McKinley are unproven and therefore uncharted territory for a company that prides itself on delivering stable, established technology platforms.

New chip microarchitectures come along every two to four years. The venerable Pentium chip, code-named "P5," was Intel?s fifth-generation chip. It debuted in 1993 and was followed by the "P6" Pentium Pro and Pentium II processors in 1995, as Intel's sixth-generation architecture. According to this naming scheme, Foster and Willamette would be the P7 generation, though Pollack declined to use this nomenclature.

Interestingly, this new architecture would appear more than five years after the P6 design, a departure from the three to four year cycle.

Willamette will be a "price-performance solution" for desktop publishing and entry-level CAD (computer aided design). Foster will be aimed at more sophisticated EDA (electronic design automation) and more demanding CAD. Willamette-based systems are expected to range from $2,000 to $3,000 in price, while Foster chips will appear in systems ranging from $3,000 to $9,000, Pollack said.

He noted that two new features of the Foster processor would be "a longer pipeline" and an "instruction trace cache." The longer pipeline allows Intel to achieve higher "clock" (megahertz) speeds, while the new type of cache eliminates performance bottlenecks in current chips.

Separately, Pollack indicated that Intel will begin integrating cache memory directly onto the processor for these 32-bit chips, and with its 64-bit chips as well. High-speed cache memory is critical for increasing chip performance in servers, workstations, and high-end PCs.

Extra cache memory is not integrated directly onto Intel processors now, but rather comes on a separate chip, with one interesting exception: the newest, low-cost Celeron chips.

When cache memory is integrated directly onto the processor, performance is better than when it is on a separate chip, as it is in the Pentium II. Ironically then, Intel?s low-end "Celeron 2" chips represent the future for Intel?s fastest, high-end silicon.

Pollack also stated that both 32-bit Foster and 64-bit McKinley will be made on an advanced 0.13 micron production process. Currently, Intel is using a "fatter" 0.25 micron process and will move later to a 0.18 micron process. Generally, with a smaller production process more transistors can be packed into the same amount of real estate, thus increasing performance. A micron is about one one-hundredth the width of a human hair.

When McKinley succeeds Merced it will split into two versions, according to Pollack. The high-end version will be targeted at the most demanding servers and workstations and a lower-end version will be "optimized for value workstations and servers," he said.

Pollack also claimed that the high-end version of McKinley would have more cache memory than any Intel chip. "Because of more integration of execution units [compared to Merced], McKinley will have the largest cache," Pollack said, implying that it would be quite large.

But before McKinley comes out, Merced chips should appear in powerful computer systems that start at about $9,000, Pollack said. Merced is due in mid-2000.

McKinley is targeted at the 1000-MHz mark and will deliver "projected performance that is 2X [two times] Merced," Pollack added.

Both Merced and McKinley will maintain compatibility with Intel's 32-bit chips.

Dispelling assertions from some analysts that Merced may only see the light of day as a test vehicle, Pollack contended that Merced is on track as "a viable commercial processor."

He also confirmed that Unix will be a key operating system for Merced. "Ask analysts--it's more scalable than [Microsoft's Windows] NT. It's important to have Unix on IA-64 [Merced]," he said.

Pollack confirmed that Tanner and Cascades chips would appear in 1999 as new members in the Pentium II and Xeon family of chips.

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