IBM said it will manufacture the new ASIC chips in volume for its Original Equipment Manufacturer (OEM) customers by January 1999. Unlike standard chips such as microprocessors, ASIC chips are designed to perform specialized functions such as manipulating 3D graphics or controlling digital cameras.
In early 1998, customers will have the software tools needed to design custom chips running between 400 and 800 MHz.
The chips initially will be used in high-end servers and data processing workstations where high performance is needed. IBM said Cray is among the interested parties.
"It's a quiet business when the world thinks in terms of Pentiums," said Joe Messingschlager, product manager in the ASIC group in Burlington, Vermont. But ASICs contribute about $1 billion in revenue to IBM, he said.
IBM is hoping the new chipmaking process--which it doesn't intend to license--will help give it a leg up in a market that Dataquest thinks could total $40 billion by the year 2001.
The "SA-27" ASIC chip will be one of the first products IBM will make using copper in the manufacturing of chip circuits. Copper conducts electricity better than aluminum, the metal traditionally used for microprocessors, resulting in smaller chips that run at higher speeds than older designs.
As companies increasingly move to differentiate their systems from those of their competitors, Messingschlager said, they are putting as many functions on ASICs as possible to save cost and space on a system's main board. IBM said the SA-27 design will be able to include up to 180 million transistors on its largest die, compared to a Pentium II processor, which has 5.5 million transistors.
IBM's Messingschlager said second- or third-generation "copper" chips should start appearing in volume applications such as engines, graphics cards, telecommunications products, and digital video processors.
In the meantime, IBM is offering an enhanced version of an existing ASIC design manufactured in the traditional aluminum process, called the SA-12E. The SA-12E will offer better performance over preceding designs by shrinking the space between transistors. IBM will be able to pack 10 million transistors on a chip it thinks will be suitable for use in handheld communications and consumer products.