IBM reveals new strain of chip power

IBM: Stretched silicon speeds chips Randy Isaac, VP, IBM Research

The company's microelectronics division on Friday revealed a new chipmaking technique it calls "strained silicon." The technique adds a latticelike layer of IBM's silicon-germanium blend to the chip, which helps to increase the efficiency of its transistors.

The technique will give a 35 percent performance boost to high-end PowerPC processors used in servers and will significantly reduce the power consumption of chips used in handheld devices, IBM executives say.

The first "strained" chips will be used in IBM servers around 2003, said Bijan Davari, vice president of technology for IBM Microelectronics. These chips will be capable of speeds ranging from 4GHz to 5GHz, he said.

IBM's PowerPC chips are still chasing the 1GHz mark. The company's line of PowerPC chips for consumer and networking purposes will hit 1GHz later this year, according to the company. Its PowerPC server chips will reach the mark with the introduction of the IBM Power4 chip, also due later in the year.

This extra performance would give IBM servers more horsepower to perform tasks such as processing e-commerce transactions and delivering Web content more quickly, the executives said.

But power-efficient chips for consumers won't be far behind. Davari says strained silicon can help create chips for handheld computers that offer gigahertz performance but consume only about half a watt of power.

Handheld computers using such chips could provide voice-driven interfaces and other advanced features to help consumers communicate more easily with a computer network.

"You can trade off the performance gain for much lower power dissipation," Davari said. "A 30 percent performance gain can be translated into two to three times (lower) power consumption."

With gigahertz processing power on tap, "you can have a handheld that can do real-time speech translation. You wouldn't need keyboards. It would just do the work," Davari said.

The strained-silicon technique gets its name from the effect it has on atoms.

A layer of latticed silicon and germanium added to the chip's silicon layer increases the distance between silicon atoms inside chip transistors. This stretching cuts down on atomic forces that cause electrons to scatter, so electrons passing by experience less resistance and flow up to 70 percent faster, providing the 35 percent performance bump.

The new manufacturing technique can be used with other IBM chipmaking improvements such as silicon on insulator, the company said.