Laptops to sport improved graphics support and an integrated 3G chip on motherboards bearing Santa Rosa technology.
Nokia's HSDPA (High-Speed Downlink Packet Access) technology will appear on motherboards bearing Intel's Santa Rosa package, Dadi Perlmutter, general manager in Intel's mobility group, said at the Intel Developer Forum here.
Notebook makers have been experimenting with integrated chips that can connect to cellular data networks, and with these plans, Intel will make Nokia's technology part of its Centrino package of chips.
Santa Rosa is the code name for the next iteration of Centrino, which blends a processor, chipset and wireless networking technology. Intel's Core 2 Duo processor, already on the market, will be joined to a new chipset called Crestline that comes with support for the company's Active Management Technology (AMT) and improved graphics performance. AMT is a nod to Intel's business customers with support for PC management technologies. The company will also move its networking chips to the faster 802.11n wireless standard.
Santa Rosa is scheduled to arrive in the first half of 2007, Perlmutter said. Around that time, Intel also plans to deliver a new chip based on a different architecture from the Core 2 Duo for ultramobile PCs, he said. This chip will consume half as much power as Intel's current mobile designs but at one-fourth the size.
Before that chip arrives, Intel will work on Santa Rosa's power consumption, using two technologies involving its front-side bus architecture and its power management controls. The company is increasing the speed of the front-side bus, which connects the processor to the memory, to 800MHz. That bus can also now dynamically scale down its operating speed, as required by the operating workload.
Also, Intel can now put its processor into a deeper sleep state, because the Crestline chipset is intelligent enough to recognize whether data is stored on the processor's on-chip cache memory or in memory. This means the chipset doesn't have to wake up the processor to check the on-chip cache memory, and waste energy.