AMD said Monday it is set to roll out its next-generation "Shanghai" chip--minus the mistakes of the last generation.
The No. 2 processor maker wants to make one thing crystal clear: Shanghai is not Barcelona. The latter chip was rolled out in September 2007 to great fanfare(or more, depending how the delay is calculated) due to production glitches and bugs. The chip was also hampered by speed (core clock frequency) limitations. This gave Intel an opportunity to regain ground it had lost to AMD in the server chip market.
"We had some mis-starts in getting Barcelona to market and wanted to bring as much velocity to Shanghai as possible. Learn from our mistakes and, as a company, never do that again," said Pat Patla, general manager of AMD's server and workstation chip business.
Shanghai--a quad-core product targeted at servers--will be AMD's first 45-nanometer processor. (Barcelona is 65-nanometer.) Typically, the smaller the geometries, the faster and more power efficient the chip. Intel has been shipping 45-nanometer processors since last year and these processors now make up most of Intel's offerings.
AMD needs Shanghai to succeed. It is
To ensure this, AMD designated a lead engineer to take over the entire Shanghai project to establish goals for the "health of the silicon, the schedule for the silicon, and the confidence level of the silicon," Patla said. AMD had to make sure that "the product that we put in the hands of our partners is going to be of substantial stability so they can do lots of early validation," he said.
As a result, the schedule for Shanghai has been pulled in. "Originally the plan was that Shanghai would launch in Q1 of '09 and we were able to pull that into Q4," according to Patla, adding that the product will not only be announced in the fourth quarter but vendors will be shipping servers in the fourth quarter.
"We're in full production right now in the factory," he said. "People will start getting first silicon from the final production very shortly."
Patla asserted that Shanghai is a "very power efficient product" and will perform much better than Barcelona because the smaller 45-nanometer process yields "a lot more (clock) frequency."
At the same frequency (speed), Shanghai will outperform Barcelona by about 20 percent, Patla said.
AMD is also boosting the size of the cache memory, which typically speeds performance, from 2 megabytes to 6 megabytes. Another speed improvement will come from increasing "instructions per clock," Patla said.
"We're also turning on HT3 (HyperTransport 3) and you'll see partners start to validate that in the Q1 time frame," Patla said. HyperTransport is a high-speed communication link technology between silicon.
Shanghai will be followed by a 45-nanometer desktop processor code-named Deneb, which is due to launch in the fourth quarter of this year or first quarter of 2009, AMD said.
In the fourth quarter of 2009, AMD will add a six-core processor. "We'll take what we've learned from our 45-nanometer process and Shanghai core and bring out an Istanbul six-core product," Patla said. Like Shanghai, this will be targeted at servers with up to eight processor sockets.