The University of Texas next week will show off TRIPS, a chip that can perform far more tasks simultaneously than other chips, although the prototype is slightly less glamorous than promised.
TRIPS, which stands for Tera-op Reliable Intelligently adaptive Processing System, is a chip architecture developed in collaboration with IBM's Austin Research Lab. The Defense Advanced Research Projects Agency is helping fund the effort with an $11.1 million grant.
The TRIPS prototype processor, which will be shown off and detailed on April 30, contains two processing cores. Each core can issue 16 operations per cycle. In all, the chip can handle 1,024 instructions at once. Most commercial chips only have a handful of instructions in flight at any given time.
At the heart of the TRIPS architecture is a new concept called "block-oriented execution," IBM said. Whereas most chips can handle just a few calculations at a time, a processor based on TRIPS architecture will be able to perform large blocks of them simultaneously, the company said.
Ultimately, the goal is to create a chip based around the TRIPS architecture that can perform one trillion operations a second, or a tera-op, by 2012. That would be supercomputer-caliber computing by today's standards.
The project was announced in 2003. Then, researchers said they were readying a prototype chip with four processor cores with the aim of creating a chip that could churn a tera-op by 2010.