Details for a second generation of the recently released G4 PowerPC processor were disclosed at the Microprocessor Forum, an annual processor industry conference here.
Among other features, the new chip will run at more than 700 MHz, according to Naras Iyengar, senior member of Motorola's Somerset Design Center. The chip also includes 256KB of secondary cache integrated onto the processor, similar to Intel's upcoming "Coppermine" processor, he said.
"What we've done is come up with a completely new microarchitecture," Iyengar said. "This architecture is capable of reaching frequencies of over 700 MHz."
It is, of course, far too early to wonder if Motorola will be able to produce enough of the chips, although the company recently was not able to make enough PowerPC G4s for Apple's latest high-end system. Motorola blamed the delay on the G4's complex production cycle.
But the firm asserted that because the problem stems from overwhelming demand for the chip, the situation is actually an endorsement of the G4 technology.
The boost in speed as well as the integration of secondary cache onto the new processor will likely serve to boost the performance of Apple desktops. Although Motorola can tout performance features of its chips that exceed the results produced by chips from Intel and AMD, the company's chips typically have lagged behind in terms of megahertz, which is used to measure chip speed.
AMD, for instance, recently released a 700-MHz Athlon, while Intel is readying a 733-MHz Coppermine Pentium III for later this month. Motorola, meanwhile, hasn't passed 500 MHz.
Running a chip at a faster frequency does improve PC performance. Further, megahertz has emerged as one of the most important factors in PC marketing, according to many. The higher number typically leads to better sales.
Motorola will be able to achieve faster speeds because of highly technical internal changes to the G4, Iyengar said. The chip will be able to process four instructions per clock cycle, up from three in the current G4s, he said. In addition, the chip will contain a seven-stage "pipeline," or data-assembly and processing line, rather than a four-stage pipeline. Longer pipelines allow designers to crank up chip core speeds.
"We've built in significant headroom for higher frequency," Iyengar said.
The chip will also contain significantly larger caches than current G4 processors. Caches serve as memory reservoirs for the processor and keep the chip fed with data. Besides the integrated secondary cache, the chip will contain 2MB of third level cache, he added.
Iyengar would not disclose a date when the second generation G4 will come out. However, he noted that Motorola disclosed the architecture for the first generation of the G4 at the 1998 Microprocessor Forum and the first chips appeared in Apple's G4 computers this past August.