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Intel's Merced alters landscape

To speed the transition to 64-bit computing, Intel is preparing a 32-bit Pentium II processor that will fit into the new Merced package.

When the 64-bit Merced processor from Intel (INTC) arrives in the second half of 1999, expect to see a number of major changes, including a wider choice of operating systems, chips that bridge 32- and 64-bit computing, processors eventually racing at speeds beyond 1,000 MHz, and a new a "slot" architecture.

To ease users into the chip's 64-bit next generation, Intel is

Planned features for Merced processor
Due 2nd half 1999
Price approximately $1,500-$2,000
Speed eventually 1,000 MHz and higher
Package "Slot M"
Floating point units 4
Markets Workstations, then servers
Transition chip Pentium II "Tanner"
preparing a 32-bit Pentium II processor that will fit into the new Merced package, sources said.

Tentatively code-named Tanner, the processor will be based around a high-speed Pentium II core but come in a probably larger Merced package referred to as "Slot M." The new slot design mirrors Intel's current strategy of first-generation Slot 1 Pentium II processors and the second-generation Slot 2 architecture.

The chip may broaden Intel's appeal on operating systems aside from Microsoft's Windows, which is by far the main platform for all Pentium processors.

Since Merced's entry point is sophisticated, high-end computers, it will run on high-end Unix operating systems as well as Windows. Sun Microsystems' Solaris, SCO Unix, and Hewlett-Packard's Unix, among others, will be equally important platforms for the processor, according Ron Curry, director of marketing for IA-64 microprocessors.

As with the Pentium II, Intel will make a variety of Merced chips, differentiated by internal chip hardware, to fit different price points. A number of the revisions result from changes in the basic processor architecture, Curry said.

Microprocessor performance improvements come from boosting speed or changing the underlying architecture, Curry said. Before 1993, about 50 percent of performance enhancements came from boosting clock speeds while the rest came from architectural changes.

Since then, however, the chip industry has relied disproportionately on changes to raw clock speed--the megahertz rating of the processor--which has stunted development somewhat, as well as limited performance.

Merced changes the underlying architectural design, bringing performance "head room" to the platform. Essentially, the new architecture compresses the branches an instruction has to follow before being executed as well as cuts down on delays between memory and the processor.

"With IA-64, we regain that 50-50 split between clock speed and architectural capabilities," Curry said.

Although he would not specify Merced's speed, he said its rates would match Digital Equipment's Alpha, slated to reach 1,000 MHz. Moreover, he said, the chip is designed with "a lot of head room," meaning that it could potentially reach speeds well beyond 1 gigahertz.

Curry was quick to point out that this "head room" also referred to architectural features unrelated to clock speed.

While he was sparse on other details, Curry did provide some clues about Merced's architecture. The chip will have four floating point units--which quadruples the number of units in current Intel chips.

Floating-point processing units are critical for extremely high-end computing and used heavily for graphical and scientific applications. Merced will also have "multiple" integer units, the mini-processors used often by business software.

Standard designs for 16-processor servers and four-processor workstations will "not be unusual" while larger multiprocessing machines will likely appear as well.

"There will be multiple configurations to target certain segments," he said. "Certainly cache is one way to differentiate in this area."

Curry would not confirm the existence of Slot M but indicated that Intel will use a different design to accommodate the larger bus. "To deliver the processor performance, you have to continue the evolution of the processor bus," he said.

With the release of the Merced class of chips, Intel is also planning a series of ancillary products--chipsets, motherboards, graphics processors--in much the same way that Intel does now.

Merced will initially see more rapid acceptance in the workstation arena, Curry predicted, because that market moves quicker than the server market.

Richard Belgard, a processor consultant, said Merced will debut on workstations costing $10,000 and up. Other innovations will appear as well, analysts say.

A significant portion of the cache memory may be integrated onto the chip silicon, said Linley Gwennap, editor in chief of the MicroDesign Resources. "You could end up with the L1 and L2 on the chip with a tertiary cache in the module," he said. Merced will likely have a 128-MHz bus.

Nathan Brookwood, semiconductor analyst at Dataquest, said that the first Merced chips will not exceed 1,000 MHz but that they will reach that point quickly.

Multiple operating systems will be another feature. "NT doesn't scale that well. I don't know if NT 5.0 will fix that," he said. "In the meantime, Unix is already there...We will see a mixture."

Intel is an investor in CNET: The Computer Network.