While Intel's upcoming Itanium chip, code-named Merced, speaks a brand-new language, IBM, Compaq Computer, Hewlett-Packard, Sun Microsystems, AMD, and other competitors are sticking with the chip architectures they already have.
Those Intel competitors laid down the gauntlet yesterday, unveiling high-end chip plans at the Microprocessor Forum here and revealing a wide variety of ways to extend their current chip designs.
Intel says those current chip designs are hobbled and don't have room to grow. But Intel's competitors, in sticking with existing designs, offer a huge benefit: They don't require software firms to overhaul their products. (When computer makers adopt a new chip architecture, all software must be reworked to fit the new design.)
"We see no need to move to a new architecture," IBM's Jim Kahle said in a talk to hundreds of chip designers at the annual processor industry conference. "Our customers demand architecture stability."
Intel acknowledges that many improvements emerged at this week's conference but said its own chips will be able to benefit from many of those design improvements in coming years. With Itanium, Intel is focusing on creating a "better building block" that later can be updated with technologies such as multiple CPUs within a single chip, said Harsh Sharangpani, principal engineer of the Itanium chip.
Ironically, the debate resembles one that began years ago when the roles were reversed. Then, Intel stuck with existing "CISC" designs while competitors shifted to new "RISC" designs.
To address performance problems, different companies are taking different approaches for chips that are scheduled to arrive in 2001 or later.
IBM, with its Power4, is putting two central processing units (CPUs) on a single chip and connecting lots of Power4 chips with super-high-speed data pathways. Compaq's Alpha EV8 chip will use a method called "symmetrical multithreading" that doubles performance with only a minor increase in the size of the chip. And HAL Computer Systems, which makes chips for Fujitsu based on Sun's Sparc designs, said some of the methods Intel is pursuing with its IA-64 chips don't provide much performance benefit.
All chips speak a language called an "instruction set," and for years Intel's chips instruction set has been known as "x86." However, with its upcoming Itanium chip--the first in a the family that uses the IA-64 instruction set--Intel is beginning a new era.
AMD, meanwhile, still sees a future in the x86 architecture. It's extending the x86 line with its own 64-bit chips, said AMD's Fred Weber, vice president of engineering for AMD's Computation Products Group.
HAL's Sparc64 V
Mike Shebanow, a designer of HAL's Sparc64 V chip due in 2001, said his company found that a method called "predication" sped up chip operations only about 5 percent. Predication is the process of writing software more efficiently before it's ever processed by the chip, avoiding situations where one calculation in the chip must await the outcome of another before it can be completed.
Shebanow, though, said his company has found it's more worthwhile for the chip to spend time on "super-speculation," executing instructions in advance, anticipating that one particular calculation is the right course of action and discarding the results if it's not.
Intel's Sharangpani, though, believes that HAL didn't have a complete use of the predication method. "You can't patch these things on and expect the benefit," he said.
Compaq's EV8 is due in 2002 and will run at speeds of 1.2 GHz to 2 GHz, said Joel Emer, principle member of Compaq's Alpha design staff. It will be manufactured with on a process capable of making features as small as 0.125 microns and will use two methods--copper interconnects and silicon-on-insultor technology--that increase a chip's speed and decrease its power consumption.
The symmetrical multithreading technique adds only 5 percent to the area of the chip, Emer said, while doubling its performance. The method essentially provides a more efficient way to feed a CPU instructions and data, filling up spare moments during which CPU is otherwise idling, Emer said.
Emer said symmetrical multithreading of using a CPU more efficiently is less costly than IBM's brute-force method of stuffing multiple CPUs in a single chip.
Indeed, Microdesign Resources analyst Keith Diefendorff said IBM's technique does use more silicon. But the symmetrical multithreading method is "more of a research thing"--in other words, a less proven idea.
IBM thinks its Power4 design is plenty good, too. Big Blue's Power4 will debut in 2001, will run at speeds of at least 1 GHz, will have 170 million transistors, and will use both silicon-on-insulator and copper interconnect technology, Kahle said.
The Power4 is a huge chip, with two CPUs connected to a large amount of high-speed memory called cache. Altogether, the package plugs into computers with 5,500 pins to transfer data--roughly 10 times as many as the Itanium.
The Power4 has very high internal data transfer speeds, Kahle said. It can move data from the cache to the CPU at speeds of 100 gigabytes per second--fast enough to transfer 20 feature movies in a single second, Kahle said