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Intel to unveil nanotechnology plans

The chip behemoth will uncork the company's nanotechnology plans at its developer conference next week in San Jose, Calif., shedding some light on the future of its chips.

Intel will unfurl its nanotechnology plans at its developer conference next week, shedding light on what will power its chips for the coming decades.
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Sunlin Chou, senior vice president of the technology and manufacturing group at Intel, will discuss the company's plans for nanotechnology, or the science of making chips with elements that measure less than 100 nanometers, next Thursday morning at the Intel Developer Forum in San Jose, California. Current chips have features measuring 130 nanometers on average.

Chou will review some of Intel's previously announced strategies for nanotechnology manufacturing, but he'll also touch on as-yet-unannounced plans in this area, according to company representatives. And right now, there are two major blank spots when it comes to Intel's nano plans: multigate transistors and carbon nanotubes.

Multigate transistors are an answer to the problems created by the shrinking size of components on a chip. Chips increasingly need greater amounts of electricity flowing through their transistors to hit their performance targets. However, transistor gates, which control the flow of electricity across transistors, measure only a few atoms thick and are getting thinner. The mismatch is akin to hooking up a fire hose to a Waterpik nozzle.

Increasing the number of gates on a transistor relieves pressure by creating more electrical conduits. IBM has already disclosed plans for double-gate transistors that will begin to appear in 2006.

"The double gate was developed in order to improve drive current," said Nathan Brookwood, an analyst at Insight 64. "While I don't think (Intel) will follow double gate, I do think they have a solution that has some similarities to it."

Carbon nanotubes, meanwhile, rewrite the basic structure of chips. With these, chipmakers would make circuits out of strings of carbon atoms rather than out of metallic wires. These carbon circuits would pave the way for smaller, faster and cheaper chips.

"It gives you the ability to conduct electricity as we can today but with smaller conductors," said Peter Glaskowsky, editor in chief of the Microprocessor Report. "The first guy to figure out how to make these consistently will be a billionaire."

Factories would also radically change. With current chipmaking methods, each transistor has to be precisely laid down through lithography, a time-consuming process that costs billions of dollars. By contrast, carbon circuits will form themselves, with the process being controlled through the laws of physics and chemistry.

Chips with carbon nanotubes, however, are still years away away.

Intel representatives declined to comment on unannounced research efforts but stated that the company would announce new nanotechnology projects, and added that the company has research under way in all of the major areas of development.

"We have our announced development approach and our unannounced development approach," said Frank Spindler, vice president in Intel's corporate technology group. "Our position gives us the potential to evaluate all of the options."

Loose lips sink chips
To date, the Santa Clara, Calif.-based chip giant has largely been a skeptic when it comes to carbon nanotubes and many other futuristic chip technologies, but that fits a pattern. Intel often publicly questions the need or urgency for new technologies while quietly integrating them into future chips.

When IBM first released silicon-on-insulator technology, an additional layer of material below the transistors which allows them to run cooler and faster, Intel said that SOI provided little benefit. Years later, the company said it would incorporate its own version of SOI into chips.

Similarly, some Intel executives in 2001 questioned the need or functionality of strained silicon, a method of improving chip performance by spacing silicon atoms farther apart. In August, the company said strained silicon would be incorporated into "Prescott," the code name of the successor to the Pentium 4, due next year.

As space age as it sounds, the nanotechnology era will actually begin in the second half of next year, when semiconductor companies begin to release their first chips made on the 90-nanometer process.

Intel's first major foray into commercial nanotechnology manufacturing will be Prescott, which will be made on the 90-nanometer process and feature strained silicon.

Subsequently, the decade will see the emergence of new types of packaging that will solve the problem of channeling substantial amounts of power into small chips, the use of optical technology inside computers and the emergence of extreme ultraviolet lithography, which uses light with a smaller wavelength to draw circuits.

Chips with multiple cores, a design technique that both conserves energy and boosts performance, will also emerge.

Also on the bill...
The four-day conference will feature a number of other announcements.

• Intel will provide updates on Madison, the successor to the Itanium II chip, due in the second half of 2003, and Banias, a new mobile chip coming in the first quarter. Both chips have been produced in samples. Banias is expected to come out at speeds hitting up to 1.6GHz.

• Intel will also give details about the upcoming 3GHz Pentium 4. Hyperthreading, a technology available in Intel's server chips, will be available "very soon," according to a source at Intel. The circuitry for enabling hyperthreading is already incorporated in the Pentium 4 but is not activated.

• The chip giant will discuss enhancements to its XScale chip, which is found inside handhelds and networking equipment. The improvements are geared toward better wireless use.

• A final, proposed specification for Serial ATA II will come out. Serial ATA connects hard drives to the rest of the computer.