The next Itanium, a major revision code-named Montecito, recently had been scheduled for debut this year, holding volume production until the first quarter of 2006 so the chipmaker can address quality problems. Now, however, it will debut in mid-2006, spokeswoman Erica Fields said Monday. Its successor, "Montvale," was pushed from late 2006 to 2007, and the next major redesign, "Tukwila," was pushed from 2007 to 2008.
In addition, Montecito won't incorporate the "Foxton" technology that would allowed the chip to run faster when it had cooled. Consequently, its top speed has been reduced from 2GHz to 1.6GHz, Fields said. Another change will be removal ofwhose front-side bus--the connection to the rest of the system--runs at 667MHz, leaving only the 400MHz and 533MHz models.
"It was required for us to do additional work to meet the production-level quality Intel is known for," Fields said of the delay, though she wouldn't detail what quality issues had emerged.
Faced with initial delays, poor performance and software incompatibility with Xeon, Intel in recent years backed off its ambition to make Itanium the processor of choice for all servers. Instead, the company tailored it for higher-end machines that compete with those using IBM's Power and mainframe chips and Sun Microsystems' Sparc line.
Hewlett-Packard, which initiated the chip project, remains a major backer, but, and Microsoft's future version of .
The Itanium delay "is generally bad news," and competitors will likely pounce all over it, said Illuminata analyst Gordon Haff, but it doesn't change the overall competition between the top server makers. "HP still has a competitive high-end processor from Intel, even with this slippage," Haff said.
HP remains "fully committed to continuing to drive positive momentum for the Itanium-based HP Integrity server family," the company said in a statement, citing 113 percent growth in Integrity revenue in the July quarter.
Things look rosier for Xeon, which enjoys widespread market popularity. However, rival Advanced Micro Devices has been gaining share with its Opteron chip.
"Breathing room" for Intel
"Intel has some breathing room, but they need to get moving," said Gartner analyst Martin Reynolds.
Intel scrapped one Xeon design, "Whitefield," and replaced it with another, "Tigerton." Both are high-end models geared for systems with four or more processors. The major difference between them is that Tigerton chips are joined to the rest of the system with a technology Intel is calling the "dedicated high-speed interconnect." With that technology, each processor will have its own connection to a computer's chipset rather than today's design, where chips share a data pathway called a front-side bus.
"Each processor has its own connection to the chipset," Field said, providing "significantly better system performance."
The high-speed interconnect is a significant change for Intel--but customers won't have to wait until 2007 to see how well they do, said one source familiar with the chipmaker's plans. In fact, the interconnect will make its debut in the second quarter of 2006 with Intel's "Dempsey" processor, a dual-core chip designed for dual-processor systems.
That change has another consequence: The delay of an Intel plan called the Common Platform Architecture that would mean Itanium and Xeon processors would share the same interconnect and chipsets. The plan would have simplified system design and been instrumental in eliminating cost differences.
The demise of the common design is less significant today than when Intel began publicizing the approach more than a year ago. "Driving down Itanium cost points so it could bring 64-bit computing for the masses--that was an important message a few years ago. It's almost irrelevant today, aside from saving Intel some engineering with joint chipset development," Haff said.
Tigerton will be succeeded by another chip in 2008 code-named Dunnington. Both chips will fit into the so-called platform, Intel's term for a chip combined with its supporting chipset. The platform is code-named Caneland.
One successful approach that AMD embraced is the inclusion of the memory controller within the processor. In contrast, Intel's approach is to build the memory controller into the attached chipset. Communication delays, called latency, decrease with the on-board controller approach. But the approach causes some timing complications when one processor needs to access data stored in memory affiliated with another processor.
Fields declined to comment on whether Caneland-based systems will use the new interconnect. But Insight 64 analyst Nathan Brookwood thinks not, expecting that Intel would love to trumpet that scenario if it could. "They're getting so beat up over it," he said.
With Caneland systems lasting through 2008, it could be 2009 before high-end Xeon chips get an on-board memory controller. But Intel could have other tricks up its sleeve.
"I think there is a reasonable probability that Tigerton and the Caneland platform do not use an on-chip memory controller. However, I think it's premature to speculate what the performance implications are without knowing a lot more about what the architecture is," Haff said.
Tigerton, like the Whitefield chip it replaces, will be built on Intel's next-generation microarchitecture, a fundamental chip design geared to consume less power and stemming from the lineage of Pentium M processors that began with "Banias."
Intel, like its competitors, is adding more processing engines, called cores, to its chips. Tigerton is a four-core processor.