Chipmakers have found it harder to kick up a processor's clock speed while actually getting more useful work out of a chip and avoiding. As a result, Intel, Sun Microsystems and Advanced Micro Devices have begun emphasizing other features--for example, squeezing multiple processing engines, called cores, onto a single slice of silicon or executing many instruction sequences, called threads, simultaneously.
But IBM announced last week at thethat its forthcoming Power6 processor will run at least at 4GHz--the same speed .
McCredie, Power6's chief architect, joined IBM's mainframe group in 1991 but later moved to its Austin, Texas, team to work on the Power processors at the heart of the company's Unix servers. IBM has steadily gained share in the Unix server market against longtime leader Sun Microsystems in recent years, and much of the future success of that competitive attack lies with McCredie.
A 4GHz minimum puts IBM ahead of the pack, but Big Blue has hit some hurdles elsewhere in the race. In 2004,, with a faster variant called Power6+ scheduled for 2007, but McCredie said Power6 now is scheduled to emerge in 2007.
McCredie spoke with CNET News.com's Stephen Shankland about papers he co-authored for the chip conference.
Q: What was the big news at the conference for IBM?
McCredie: The main thing we did here is reveal the Power6 system design. We're still a year away from general availability, but the message we're trying to put out is we're still on schedule and continuing our pace. We released Power4 in 2001, Power5 in 2004, and we're on track for 2007 for Power6. We were showing pass-two (second-generation prototype) hardware results in all our papers with performance numbers. We're hitting some high-frequency targets.
Many of your rivals say they're moving on from the clock speed race.
McCredie: The high frequency is a real strong message out there. Other people may be shying away from high frequency, but we're still focusing on that. We didn't go to extremely power-hungry circuits or slicing the pipeline into 20, 30 or 40 stages, which implies you got the frequency by sacrificing performance.
A deeper pipeline divides up processing into many different steps so several instructions can be processed at the same time.
McCredie: The pipeline is the measure of the delay from the point where instruction is launched to point where an application or user has access to the results. (Having a deeper pipeline) is like having several sinks to wash the dishes--one for washing, a first rinse, a second rinse...If you hit the high frequency by really lengthening the pipe, you increase how long it takes for an instruction to get through the computation. If you double your frequency and double your pipe depth, you don't deliver a lot more performance. We doubled the frequency but held the pipe depth the same as Power5.
Power6 is built with a more advanced manufacturing process employing 65-nanometer features compared to the 90-nanometer process of Power5+. (A nanometer is a billionth of a meter; smaller circuitry means chips can be made smaller and more cheaply.) How is the 65-nanometer process working out?
McCredie: Right now we're very pleased with 65 nanometers. It's coming along nicely, as you can see from the frequency number. On one paper we showed the maximum frequency reached 5.1GHz. We got a little better than 2x the performance, which shows the 65-nanometer process is performing better than our 90 nanometer.