SAN JOSE, California--Advanced Micro Devices provided details surrounding its next generation microprocessor, the K7, today at the Microprocessor Forum in San Jose, California, while Intel and National Semiconductor also unveiled chip designs.
Among other features, the K7 will run at 500 MHz and higher and use a new technology for the "system bus," a critical data conduit which allows the processor to talk to other components in the computer.
By 2000, it will run at 1000 MHz, the company has said.
Intel today spelled out its future Katmai chip technology. The Katmai Pentium II processors due in the first quarter of 1999 will provide a boost to how 3D graphics and video data get viewed and manipulated on standard PCs. (See related story.) Katmai technology has also been referred to as "MMX 2," which is the successor to Intel's current MMX technology found in Pentium II processors.
The upshot: Streams of images will run more smoothly when replayed, or edited, on Katmai-enabled programs on Katmai-based PCs.
Intel is also expected to provide more details on its 64-bit Merced chip, as well as more on the recently unveiled plans for the Willamette and Foster chips that will succeed the Pentium II and Xeon chip families in 2001. Foster chips represent a spanking new 32-bit chip architecture for Intel.
As a counter thrust to Intel, AMD said today it is launching its own architecture with the K7. The chip will come out at the end of the first half of 1999 with a 200-MHz system bus licensed from Digital that is capable of being boosted to 400 MHz, according to Dirk Meyer, director of engineering at AMD.
Intel's fastest system bus today runs at 100 MHz, although 133 MHz and 200 MHz are expected in the future.
The chip will also be capable of multiprocessing, a new segment for AMD.
The K7 will come with a large secondary cache--high-speed memory for boosting chip performance--that will not initially be integrated into the processor. Most vendors are moving to a design where 128KB (kilobytes) or 256KB of performance enhancing cache memory is fused into the same piece of silicon as the processor. In fact, virtually all chips will have integrated secondary caches by 2000, said Michael Slater, founder of MicroDesign Resources. AMD is bringing out an integrated chip with the K6-3 processor later this year.
The K7, however, will have a separate secondary cache, which will make it similar in design to current Pentium IIs. The secondary cache will range in size from 512KB to a whopping 8MB (megabytes), said Meyer. The K7 will not integrate a memory controller like lower-end chips, he said. The cache will run at a fraction of the processor speed, predicted sources.
While a separate, non-integrated cache takes away some performance, the move will allow AMD to hit a wider variety of markets, said Dean McCarron, principal analyst at Mercury Research. Lower-end K7s, for example, can be made cheaper by using standard SRAM cache chips rather than the specialized ones used in high-end Intel processors. More expensive versions will likely support faster memory.
"We want to sell the K7 into a couple of markets. With the K7, we want to be in a position to address markets that we haven't before." explained Meyer, adding, "memory technology is in a state of transition."
The risk for AMD is whether the industry will support the chip. Because the K7 does not use an Intel Pentium- or Pentium II-design system bus, AMD will have to persuade PC circuit board and companion chip vendors to build products that can only be used with the K7.
"The question for them is the infrastructure issue," said McCarron. Like other observers, McCarron said that this support will build, but the pace is difficult to gauge.
Meyer, for his part, said that the company is getting a good reception for the product from its current chipset and motherboard providers. Sales of the K6 chip, he said, have strengthened the support of these companies.
Meanwhile, lower-end processors, such as the Jalapeno processor from National, will incorporate features such as 2D graphics while its successor, the M3, will add 3D, video decoding (playback) and encoding (for creating video), as well as modems for maximized performance in different segments for 1999.
The first "completely new architecture from Cyrix since the original 6x86 processor" Jalapeno will run at 600 MHz and higher, according to Cyrix.
The Jalapeno design includes an 11-stage deep-pipeline--which allows Cyrix to boost clock (megahertz) speeds--and a completely new floating point unit, in addition to the 3D graphics features.
"This latest core technology will be the soul of the M3, Cyrix's next-generation processor, expected to debut in the fourth quarter of 1999 in the 600-800 MHz speed range," Cyrix said.
Intel will not incorporate graphics into its Celeron chips, but will come out with Whitney, a companion chipset for low-cost systems with integrated 3D.
Intel's future performance desktop chips will emphasize the new Katmai instructions, a new series of floating point instructions that will enhance graphics and video by managing memory better. AMD, meanwhile, will likely continue to push its 3D Now! Technology, but also adopt Katmai, said MicroDesign Resources' Slater.
"I think we will see a combination of 3D Now and Katmai in these competing processors," said Slater.
"There is a diversity of design focus," said Slater. This will create expenses for motherboard vendors, but create opportunities for "maximization for specific tasks."
|Chips for the next millennium|
|Celeron||Desktop||366 MHz||Q1 99|
|Katmai||Desktop||450 MHz||Q1 99|
|Tanner||Workstations||500 MHz||1H 99|
|Coppermine||Desktop||600 MHz||2H 99|
|Cascades||Servers||600 MHz||2H 99|
|K6-2||Desktop||400 MHz||Q4 98|
|K6-3||Desktop||450 MHz||Q1 99|
|Jalapeno||Desktop||600 MHz||Q4 99||Source: Various|