CNET también está disponible en español.

Ir a español

Don't show this again

Tech Industry

AMD sets date for son of Opteron

The chipmaker is "working like crazy" on a new architecture for the successor to Opteron and expects to release the chip by the end of 2005, according to an Advanced Micro Devices executive.

SAN JOSE, Calif.--Advanced Micro Devices, which released its Opteron chip only six months ago, is already planning to come out with a successor in 2005.

The Sunnyvale, Calif.-based company is "working like crazy" on the K9, an underlying architecture, or blueprint, for a new generation of chips, said Fred Weber, chief technology officer of AMD's computational products group, during an interview at the Microprocessor Forum here Wednesday.

Chips based on the K9 architecture will likely be released--at least in sample quantities--by the second half of 2005, Weber said. AMD engineer Randy Allen is overseeing the project.

Chip companies release new architectures every three to four years, but the process is becoming increasingly difficult because of power consumption and the shrinking size of transistors. The K8 architecture, the basis for the Opteron released in 2003, was unveiled in 1999 by Weber at the same conference. Chips based on the K8 design were originally due at the end of 2001.

Although Weber declined to provide technical details about the K9, processors that are based on the architecture will likely be capable of containing multiple chip cores--the "brain" of the chip--and of running one or more application threads. Putting more than one core inside the processor boosts performance in a relatively efficient way, Weber and others at the conference said. Opteron, in fact, is designed in a way that enables a second core to be added, Weber noted.

"We will have a multicore product," Weber said.

AMD is also looking at adding threading to future chips. Simultaneous multithreading essentially enables a chip to run two applications, or two "threads" of the same application, at the same time--thereby reducing the time it requires to complete a task. Threading, however, does not provide as much of an improvement to overall performance as multicore technology does, according to Weber.

Most chips that come out over the next few years will likely feature a host of new materials and structures, such as multiple-gate transistors and strained silicon layers, according to analysts.

x86 marks the spot
Separately, in a keynote speech at the conference, Weber sketched out a future of computing in which most computers, handhelds, cell phones and other devices will rely on processors based on the so-called x86 architecture. The overall x86 architecture is at the heart of chips made by Intel, AMD and a few other small companies, with K8, K9 and Intel's NetBurst architectures being x86 derivatives.

The reason for x86's rise, he said, comes down to history. Most software is written for chips based on the x86 architecture, which is also the oldest microprocessor architecture. There is also a great diversity of x86 chips.

"The time is right for x86 processors in all form factors," Weber asserted. "Because of its dominance on the desktop, it has grown to have the vast majority of software."

In contrast, the RISC architecture, at the root of chips from Sun Microsystems, IBM, Hewlett-Packard and ARM, isn't proliferating at the same rate. General sales trends back this up. RISC servers, once the mainstay of the market, now account for only around 12 percent of unit sales and less than half of sales as measured by revenue, according to analysts. It is, however, still dominant in cell phones.

Weber's partisan speech in many ways complemented and contrasted with the boosterish keynote speech Sun CTO Greg Papadopoulos presented yesterday at the conference. Papadopoulos said microprocessors are "dead" and will be replaced by microsystems, which are essentially complete computers on a single piece of silicon. These microsystems will then exchange data over a network.

Weber agreed that more functions would continue to be added to microprocessors but said microprocessors or microsystems--functionally the same thing--will need to speak the same language, which will be x86.

Invite Michael Kanellos into your in-box
Senior department editor Michael Kanellos scrutinizes the hardware industry in a weekly column that ranges from chips to servers and other critical business systems. Enterprise Hardware every Wednesday.




Porting, or rewriting, software to ensure that it runs on RISC or other architectures is largely money down the drain, Weber said. Many RISC-based projects, such as corporate projects aimed at giving many employees RISC-based handhelds, often fail because of software compatibility issues.

"Porting is not just porting the application. It is porting the OS, the tools, the drivers the codex," Weber said. "It is pretty clear that this does not work."

By analogy, Weber said before the advent of a common currency in Europe, Europeans spent $36 billion a year on exchanging money, or $90 per person.

Critics have often complained about the structure of the x86 architecture and the complexities that have crept into it over time, Weber noted.

"I call the x86 a Baroque architecture. It is all full of geegaws and curlicues, but it is pretty structured in the end," he said. "It is not necessarily the instruction set you would choose if you were starting from scratch, but it is not necessarily a wrong one."

Like others at the conference, Weber said chip designers have a number of problems to tackle. Chips will increasingly contain multiple processing cores, with each core handling two or more application threads at the same time, he said. Power consumption and memory latency, or the time it takes to get data out of memory, will continue to be major bottlenecks.

"We've hit the memory wall," Weber said.

Still, the problems are not insurmountable. Moore's Law, which states that the number of transistors on a given chip can be doubled every two years, has a lot of life left in it, Weber said. Designers will likely continue to increase the number of transistors on a chip by stacking them.