At the Microprocessor Forum here this week, AMD's chief technology officer, Fred Weber, said that during tests in the company's labs, a server running a 2GHz Opteron achieved an "estimated" SPECint 2000 score of 1,202 and an estimated SPECfp 2000 score of 1,170, higher than most competing chips on the market today.
The score on the SPECint benchmark, which measures how rapidly the chip processes integer calculations, is particularly interesting because server customers look at the figure when considering purchases. Most SPECint scores today are below 1,000, noted Nathan Brookwood, an analyst at Insight 64. SPECfp is used to judge mathematical abilities more relevant to workstations or supercomputers.
Also at the industry confab, Intel discussed how it might construct a chip containing multiple Itanium cores (a core is the computing engine on a processor).
Although the AMD benchmarks were produced in lab conditions, and Weber declined to elaborate on the technical details behind the server and chip used in the tests, the scores indicate that the chip is more or less hitting the early performance claims made by AMD. The benchmark figures could help the company in itsto get its into the mainstream server market.
Sources who requested anonymity, however, said the figures have to be taken with a large grain of salt. Outside of AMD's labs, not many have had an opportunity to play with the Opteron or other members of the Hammer family.
Other than the test scores, Sunnyvale, Calif.-based AMD kept a tight lid on details surrounding Opteron and other members of the Hammer line.
Opteron will appear in the first half of 2003, said Mark Bode, division marketing manager of the desktop products group at the company. Bode said theof Hammer will hit shelves in March or April and the notebook version, like Opteron, will publicly debut sometime in the first half.
Although Weber discussed a 2GHz Opteron, the company has not committed to releasing the chip at that speed. Analysts have said the first chip could run at speeds between 2GHz and 2.4GHz. AMD earlier said the chip would be marketed with a 3400+ performance number.
The Hammer family will be able to run both 32-bit software, the kind found on desktops today, and 64-bit software, found on high-end servers. Although 64-bit software won't be common for years in the desktop world, where the vast majority of AMD's chips are sold, the ambidextrous nature of the processor means AMD will be ready when desktops finally make the jump.
"Will it be in 2005, or 2006 or 2007? It is not clear, but it is in that time frame," Weber said.
By contrast, Intel has separate chip families for the 32-bit world and the 64-bit world, a situation AMD's Weber called "a house of cards" during a panel speech. Intel declined to respond to the comment, but stated that it is committed to its chip families.
Split Itanium personality
In its presentation, Intel discussed how it might construct a multicore Itanium chip. The company has already said it will come out with multicore chips, but hasn't said how they might be built.
Multicore chips are becoming a reality because by 2007 chips will have a billion transistors, and you have to do something with all those wires, said John Crawford, a Fellow in Intel's Enterprise Group.
Using 1 billion transistors, Intel could put four separate Itanium cores onto a chip, Crawford said. These cores would then share a common cache, similar to IBM's Power4 on sale today.
A mega-chip of this sort could benefit computer designers in a number of ways. A four-processor server would be far easier to construct because it would require far fewer chips. Applications could also jump from one core to another to avoid building up "hot spots," Crawford added. Intel has discussed suchtechnology in the past.
"We are spreading out hot spots across the die into four areas," Crawford said. He didn't say Intel would actually make an Itanium with four brains, but he said that it was "eminently doable." Other Intel executives have said multicore chips are inevitable.
The billion transistor budget could also be use to build encryption functions right into a chip and to create better processing for .Net and Java, Crawford added.