Chief Technology Officer Justin Rattner unveiled the name and several performance and power details of processors using the design at thehere. The architecture, derived from the design of the Pentium M processor, puts a major emphasis on lowering power consumption and the older priority of boosting performance.
"Energy is on everyone's mind. It's the next frontier. Not only has it become a critical concern in our daily lives, it's become a critical concern in just about every platform we have," Rattner said in a speech at the show.
The Core microarchitecture is designed to deal with two related pains in computing,. Improving performance per watt gives Intel a new sales pitch at a time when it faces compounded by .
The Core microarchitecture is the sequel to the ill-fated NetBurst microarchitecture used in Intel's Pentium 4 lineage. NetBurst was focused on achieving high clock speeds, but it drew inordinate amounts of power at fast speeds and Intel canceled its plans to take the design to 4GHz.
"When the Pentium 4 first came out, the performance was very disappointing to a lot of people initially," Illuminata analyst Gordon Haff said. "It's hard to call the Pentium 4 a failure, given how many they sold, but it was certainly an evolutionary dead end."
Three chips based on the Core microarchitecture--all dual-core models--are planned for the second half of 2006: Conroe for desktop computers, Merom for laptops, and Woodcrest for servers. Rattner touted improvements coming with all three.
Woodcrest will boost performance 80 percent while reducing power consumption 35 percent compared with a, he said. Conroe will boost performance 40 percent and decrease power consumption 40 percent compared with a dual-core Pentium D 950. And for Merom, customers should expect "handsome gains relative to the Core Duo T2600 while maintaining the same battery life," he said.
Cutting energy consumption
Rattner showed a chart of several Pentium processor generations illustrating that gradual performance improvements were offset by growing energy consumption demands.
"We've been studying this for years, and the trend was a bit alarming," Rattner said. "The amount of energy required to execute a single instruction has increased significantly--well over a factor of four over this time frame."
The original Pentium in 1993 consumed about 13 nanojoules for instruction it executed. The Pentium Pro in 1995 nearly doubled performance, but consumed about 24 nanojoules per instruction.
The Pentium 4 in 2001 was about three times the performance of Pentium, but it consumed about 38 nanojoules per instruction, while the Pentium 4 had four times the performance but about 49 nanojoules per watt.
The Pentium M lineage of chips originally designed for mobile PCs changed the trend. The first model in 2003 had the same 12 nanojoules per instruction energy consumption as the original Pentium but about 2.7 times the performance. Core Duo, which came to market this year, has four times the performance and even lower per-instruction consumption of 10 nanojoules, Rattner said.
The processor is only one component in a computer, though. Intel is working on reducing power demands for the rest of the system through technology called extended idle mode, Rattner said. Processors can shut down when idle, but this technology lets other parts do the same.
One part of extended idle mode is display self-refresh, which sidesteps the need to wake up the whole system just to update a computer's display. It even can run with the motherboard turned off as long as the display image isn't changing, Rattner said.
"The potential for managing power at the platform level is really great. It's something we need to address for all our systems," he said.
Core microarchitecture features
Rattner touted a list of improvements coming with the new chip design.
Intel Wide Dynamic Execution, which lets as many as four instructions be executed in a single tick of a chip's clock. In addition, a feature called macrofusion automatically combines two high-level chip instructions, in some cases into a single instruction.
The Digital Media Boost means all "SSE" instructions can execute in a single clock tick. SSE stands for streaming SIMD (single instruction, multiple data) extensions and speeds several operations such as video decoding or digital photo processing.
Intel Advanced Smart Cache improves how high-speed cache memory is shared by multiple processor cores. For example, it lets one core control the whole cache when the other core is idle, and for other times, it governs how the same data can be shared by both cores, Rattner said.
Intel Smart Memory Access is an improved set of algorithms that can predict what data should be "prefetched" from main memory into faster cache memory so it's at hand when the processor needs it, he said.
And Intel Intelligent Power Capability "lets us shut down portions of the chip that aren't needed at a particular time to support instruction execution," Rattner said.
New manufacturing process
Rattner also touted Intel's manufacturing prowess. The company started building chips using a manufacturing process with circuitry features measuring 65 nanometers last year, and the next-generation 45-nanometer chips are well under way. in January.
"We believe we're over a year ahead of the competition in delivering 65-nanometer technology. In the second half of 2007, we'll move to 45-nanometer technology," Rattner said. The memory chip prototype "has given us great confidence in the success of 45-nanometer technology," which will permit larger onboard high-speed memory caches and more processing cores on a single chip, he said.
But he indicated Intel isn't racing to build eight-core chips.
, but that should satisfy the multicore demands until software catches up to the approach, Rattner said. Doubling from dual-core in 2006 to quad-core in 2007 made sense, he said, but added, "Will we double again in 2008? Probably not."
"Intel is taking a conservative approach that focuses on single-thread performance," he said, though he didn't mention competition from Sun Microsystems'. "You won't see mediocre thread performance just for the sake of getting multiple cores on a die," he said.
He also urged software companies to work on supporting multicore designs with software that can divide tasks among multiple execution threads. "It's really time to get onboard the multithreaded train," he said.