An Intel paper to be released Tuesday offers more details on future Nehalem processors.
Rajesh Kumar, Intel fellow and director of the Circuit & Low Power Technologies Digital Enterprise Group, gave a brief overview of a paper covering "clocking architecture" and some of the major data transfer and power savings goals for Nehalem, Intel's next-generation chip architecture due in the fourth quarter of this year. One of Nehalem's major new features is QuickPath (PDF), a data transfer technology.
He began by explaining why Nehalem integrates more components--including the memory controller--than previous Intel chips. "The reason we are doing this is to get lower latency to memory. And much higher bandwidth to memory," he said.
Kumar said Nehalem will deliver "25 gigabytes per second for socket to socket (chip to chip) communication. And 32 gigabytes per second going to main memory."
"We're about 3X faster than our competition today," he claimed.
He also described how Intel is doing more to optimize power saving over previous generations of processors. "The number of cores and most of its features are modular. You can change the number of cores in different segments, for example. But just doing that is not sufficient. Because we're going to emphasize energy efficiency for some cases and high performance for others, we also needed to makes these things scalable," he said.
He went on to describe how the processors can be scaled for different markets. "As a result, we had to make all the main components work in a decoupled fashion. Such that frequencies and voltages can all be set independently. The CPU core, for example, can be running at its own frequency and voltage, while the memory system is running on its own, and the I/O (Input/Output) is running on its own, and each of them can be tuned for a given segment."
Kumar said the technology itself isn't new, but that Intel's technique is different than its competitors. "The idea itself is not new but the implementation is new. So far, most people that have tried this idea have done this using what are called asynchronous interfaces which happen to be fairly slow. So the main idea is how to do all of this in a synchronous fashion with very low latency and high performance," he said.
He also described how Nehalem chips are better tuned to operate based on the level of power delivered. "Chips today run at a given frequency, at a given voltage. But we know that when running different applications the power supply keeps moving around," he said. "What we have introduced is a chip whose frequency keeps adapting every cycle to the dynamic and real time power supply it actually sees."
In related news. Chinese-language Website HKEPC is showing three versions of the Nehalem processor. The "Bloomfield" XE running at 3.2GHz, another running at 2.93GHz, and third at 2.66GHz. All have four processing cores that run eight threads, all have 8MB of level-3 cache memory, and all have a thermal envelope of 130 watts.
The XE has a QuickPath data transfer rate of 6.4 gigatransfers per second (GTs). The other two deliver 4.8GTs.
All are due in the fourth quarter.