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IBM, Intel to tip on energy-saving chips

At the International Solid State Circuits Conference in San Francisco, Intel, IBM and other companies will talk about how future processors will run faster on less energy.

Intel, IBM and other semiconductor companies will provide details on how future chips will run faster on less energy at the International Solid State Circuits Conference in San Francisco this week.

Energy has become an overriding obsession for chip designers in the past two years. Chips are continually getting smaller and more powerful, which means they consume more electricity and produce more heat. To prevent the computers of the future from melting, engineers are experimenting with circuit designs, packaging techniques, insulating materials and other elements to run chips on less energy.

"It has gone from an era where you didn't have to think about (energy) to an era where everyone thinks about it," said Russell Lange, chief technology officer of IBM's Technology Group. In earlier times, in fact, companies would brag about the amount of electricity a mainframe required, Lange recalled.

High-tech companies and academic researchers use the ISSC conference to deliver papers on scientific breakthroughs that will likely get adopted into products in the relatively near future.

Intel, which has showcased a number of energy-saving techniques in the past year, also will present papers on ovonics, a venture in which it hopes to make memory chips out of a new material--that used in compact discs.

The PC chip giant will present a paper on how energy can be conserved through "body bias." Body bias refers to the direction in which select circuits are pointed. In forward body bias, where the circuits point to the "forward" edge of a chip, power consumption can be cut by 23 percent, said Justin Rattner, an Intel fellow.

By reducing power consumption, Intel can raise the performance ceiling. In its labs, it has managed to run an arithmetic logic unit, an architectural element found in processors, at 10GHz on 1.66 volts, Rattner said.

Reverse body bias can also reduce leakage, or current that escapes from circuits, by 3.5 times. Adopting bias can also increase the yield, or percentage of good chips culled from an individual wafer.

Chips containing bias could show up when Intel moves to the 90-nanometer manufacturing process, which begins in 2005, or, more likely, when it moves to the 65-nanometer manufacturing process two years later. Incorporating the technology should be relatively inexpensive, Rattner said.

Ovonics memory chips, meanwhile, use diodes rather than standard transistors to transmit signals. They won't transfer data through optical transmissions--electrical connections will still be required--but the chips will be much faster than conventional flash memory. Like flash, though, ovonics chips will retain data stored on them when a device goes off.

"It will come close to ideal memory," said Stefan Lai, another Intel fellow.

Still, the work is far from over. These chips, he added, consume a lot of electricity. The company has produced a 4MB ovonics cell using the 180-nanometer production process and will come out with a 130-nanometer version in 12 months. Product plans are still far off.

"There have been attempts to made diodes into memory before," he said.

IBM, meanwhile, will present papers on two low-power PowerPC chips. In one paper, IBM will describe how it has greatly reduced power consumption on a 1GHz PowerPC 750 through frequency scaling, or reducing the clock speed at various times. Subsections of the chip also shut of automatically when not in use to reduce power consumption.

IBM adopts techniques touted by Transmeta and Intel but achieves better results, Lange claimed.

In its other low-power paper, IBM will lay out the details of a PowerPC 405LP that the company says consumes so little power that it will be appropriate for use in handhelds.

"It's easy to adjust the power. What's not easy is to do it in a way that doesn't interfere with the performance of the processor," Lange said.