Code-named Avebury, the company's upcoming chip contains 96 separate internal units tuned for doing particular types of math problems. Inserted into Intel- or Advanced Micro Device-based servers, Avebury will handle the repetitive, computational grunt work involved in preparing a study on how a single protein will react with thousands of others or a financial analysis that charts how slight changes in a stock portfolio could affect a person's financial position over the course of several years.
"This allows for local, high-performance computing, so technical users can complete their work on a small cluster or their desktop," said David Hoff, director of technical marketing at ClearSpeed, which has offices in Los Gatos, Calif., and Bristol, England.
Chips that help a computer's main microprocessors perform specific types of math problems are becoming a big business once again, decades after companies like Intel integrated these chips into main microprocessors to cut costs.
RIKEN, an anglicized acronym for Japan's Institute of Physical and Chemical Research, revealed details earlier this summer about a that can perform a quadrillion operations per second. That's more than existing supercomputers, although the MDGrape 3 can only handle certain types of functions.
, meanwhile, recently announced it is concocting a chip with 24 processing cores for accelerating Java applications.
The driving force behind the move to co-processors is . General-purpose high-end microprocessors run in the 3GHz range. Partly as a result, some of these chips require 100 watts or more of power, more than household light bulbs, and generate tremendous amounts of heat.
Co-processors conserve energy by running at lower speeds but performing more tasks at the same time. Avebury, for instance, runs at 250MHz and coasts on 5 watts. But with its 96 processing cores, it can churn 50 billion floating point operations (math problems that involve a decimal point) per second. A typical microprocessor on the market today will have three floating point units and generally perform less than 10 billion operations per second.
The architecture works because the underlying equations in instructions in many applications are often identical--only the numerical variables change. In biological research, for instance, scientists will prepare data on the hundreds of different ways a single protein can be folded, and then need the same exact corpus of data on folding for thousands of separate proteins.
Currently, several national labs, some oil companies and a few universities are experimenting with Avebury, Hoff said.
Another benefit comes in gradual degradation. If a single processing element burns out or fails to work, the remaining 95 will continue to function. At that point, the chip will provide slightly less performance, or can be sped up to compensate for a loss of performance.
Handing off work
is currently working with software developers and hardware makers to optimize their products so that the main microprocessor will hand off this sort of work to the co-processor.
"The application has to be accelerated ahead of time," Hoff said. "They need to be recompiled."
The company last year came out with a chip with 64 computing cores, called the CS-301, to seed the market. Avebury not only increased the number of computing cores by 50 percent, it runs at a slight faster speed. Despite the addition of the new processing cores, the older and newer chips are the same size.
"The CS-301 was never optimized for cost or real estate," Hoff said.
Samples of Avebury now exist. Commercially available versions, which will then be called CSX-600, will come out in the first quarter of 2005. IBM's Semiconductor unit serves as the foundry.
Hoff, though, added that Avebury isn't for bargain hunters. A workstation that contains a dual-Avebury card will likely cost around $50,000.
"Not everyone is going to buy that for their home today," he said.