Appointed in September, Hester is taking on full force the future of AMD's processor designs. He replaced, a man who many credit with the development of AMD's Opteron chip, a key piece in the Sunnyvale, Calif.-based chipmaker's turnaround.
CNET News.com recently spoke with Hester about AMD's plan to offer quad-core processors by 2007; migrate to DDR2 (a computer memory technology that, as of 2005, is becoming the mainstream standard for personal computer memory); and his vision of the next generation of Opteron and Athlon processors, including building the company's ecosystem by licensing its technology.
Q: Is it true that AMD is looking at licensing parts of its
Hester: The idea has been around for a while but it relates to understanding what our direct customers and the end customers want to do. The idea is to selectively license the coherent HyperTransport technology (a chip-to-chip interconnect supported by AMD and primarily used on a computer system board in distances up to 24 inches).
Isn't this the technology that you have been promoting for years as a better alternative to Intel's front-side bus systems or its upcoming Common System Interconnect?
Hester: Right. So the example I'd give you is in the high-performance tactical computing area, where people like Cray and others would like to do vector floating-point units.
Being able to do that requires a co-processor, or attached processor elements that would attach into a standard system. We don't have any finalized plans yet, but if you look at the workloads in the data center, you're starting to see applications where, if you could accelerate XML and Java, a number of the vertical applications would perform significantly better. So instead of trying to build a machine that's just aimed at workloads, you can think about the attached processor or co-processor that works in conjunction with our AMD64 architecture to accelerate those workloads.
Can you paint a picture of how it would look on the motherboard?
Hester: The simplest way to think about it is to build an eight-way symmetric multiprocessor system based on AMD64 processors such as Opteron. Think about the ability to replace one of those with a specialized engine. This chip is really aimed at running a specific workload like vector floating-point or XML or Java.
Is that technique possible today without letting that partner have knowledge of how AMD uses HyperTransport?
Hester: No, you would have to have detailed knowledge in the form of a license for the coherent HyperTransport.
How is this going to be a good competitive advantage for AMD's
Hester: This is the concept of a friendly ecosystem that today, if you want to go build a specialized system, you really have to build all of it. Instead of building all the hardware infrastructure and the software infrastructure to support it, the idea here is that it's a lot less development expense and, in my opinion, a lot easier to leverage the standard software infrastructure that's there.
Is this a radical shift in AMD's strategy?
Hester: Yes and no. The nice thing about this is the AMD64 design is a reliable, high-volume cross-platform. The ecosystem is in place to support that already because it's fully compatible over the Linux and Microsoft software out there. It's also nondisruptive as you kind of move upstream. That is not the case with Itanium, for example.
I think AMD now is at the point that the base hardware level is very competitive, and the question for us now is, "Okay, you have a great platform; now what do you do?" And so my bias is, once you got a base platform, you want to effectively then build on that very quickly at all levels. There'll be elements of that or hardware-enabling technologies like a license to coherent HyperTransport. There'll be work we'll do with Microsoft and the software Linux community to deal with things like ease-of-use or reliability features and recovery, and virtualization partitioning. So to me, it's the next level of focus in the industry, beyond just the raw silicon level.
Let's talk about AMD's raw silicon level. Opteron and Athlon chip architectures are based on your K8 designs, previously called Hammer. Is there a K9--or Hammer 2--in the works?
Hester: There's kind of two separate discussions related to that question. One is the software-visible instruction set architecture, the ISA. The second thing is the internal architecture of how you actually implement that in silicon, and so those two things are separable.
Let me give you some examples. If you look at what we're doing around virtualization and security onand , those were instruction set architecture (ISA) extensions. Obviously, hardware changes are needed under the covers to implement that, but there are those who have done so largely around the microarchitecture code that exists today. So, AMD's kind of manufacturing in strategy is roughly every quarter we've got a higher performance transistor and so you kind of keep the same underlined microarchitecture and incrementally improve new manufacturing technology. So, the structure of the microarchitecture largely stays the same.
Then there is a brand new core design that has to be fully backwards compatible with the old instruction set architecture. Then you can also choose to introduce new instruction set extensions at the time of that new core. So, what you typically see is a core that lives--depending on the market segment--two to four years, and so then you want to time the introduction of a new core with major changes that you need at the system level.
At that point, you could look at things like next-generation memory technology. There'll be cases where you'd want to introduce a new generation core along with the new memory technology. There will be other cases where, for example--and that's the case right now that lot of people told us--they want to keep the same base design that we've got, but go to DDR2 (Double Data Rate RAM) as opposed to Intel's FB-DIMMs (Fully-Buffered Dual Inline Memory Module). So it's really kind of listening to the ecosystem about what they want to see from us in a road map.
We have a menu of things that we can do both incrementally and with new cores that are cause for discussions. So right now, our belief is that through the 2007 time frame, using new implementations of the existing core with extensions and memory technology is the right answer. Then, roughly in 2007, we'll see the introduction of a brand new core design kind of under the covers.Does that include a plan to offer quad-core processors by 2007?
It seems that Intel has got a lot of different products coming right out of the gate in 2006, whereas--and this is the perception by some analysts--AMD will still be sitting on the same technology early next year.
Hester: I give Intel great credit for creating a myth. (laughs)
They've canceled a heck of a lot more projects than we've canceled. What I hear is the other guy is showing stuff that they're not going to ship for six to nine months and then comparing it to our stuff that's shipping today. What we showed in the analyst meeting was a road map that says, "Look guys, we have a track record of delivering improved performance every quarter." And so, if they're showing stuff that's six to nine months away, that's two to three of our steps away. And so, if they're having to show six-to-nine-months stuff against ours and saying it's kind of competitive to what we've got today, then by the time we get there, the shipping gap should be the same as the shipping gap today. So Intel, show me what it is that you're specifically going to deliver to the market that changes this.
Another point that analysts point to is that Intel has an advantage in bringing 65-nanometer process technology to the semiconductor market faster.
Hester: There are two pieces to that statement. The first part focuses on when Intel will ship its first 65-nanometer technology. The second piece of that statement questions when Intel's promise really yields in shipments and volume. AMD's philosophy is fundamentally different than Intel's. AMD tends to not buy the newest technology at the earliest possible date it's available. We tend to buy the technology a little bit later. The processes we put in place are focused around what we call automated precision manufacturing. What it allows us to do is tune the manufacturing process much tighter than when a general layer of silicon line is run.
So if you look at the yield ramps in terms of the time that it takes from when you start producing the technology until it hits essentially sustainable manufacturing yields, that time for AMD is much faster than for someone else. So the question to me is not necessarily when you introduce the technology. I mean if you want to ship when you have very limited volumes, that's one discussion. The other discussion is when that technology is broadly shipping in the industry.
From that perspective, I think we're in the position we need to be; we're fine. Besides, the last time I looked, people don't buy nanometers, they buy end-user performance.
The man you're replacing as chief technology officer, Fred Weber, is called by many people the father of Opteron. What kinds of conversations did you two have before he left, and what advice did he give you?
Hester: Fred and I have known each other for some time, so this was not a surprise that he was going to go do some other stuff in the venture capital world. But his thought was that I should continue to build on what he established.
Did he put his arm around you and say something like, "All right kid, I worked hard on this. Don't screw it up?"
Hester: Fred has done a great job. I won't screw it up. (laughs)
Hester: I have no idea. I think Kevin's decision on AMD is a business decision, not a technical decision. That's my personal opinion.
Suppose Dell adopts AMD chips in volume amounts. Do you have a
personal opinion about being able to supply this new wave of customers? There was some concern before Fab 36 in Dresden opened that you weren't going to be able to make enough.
Hester: I think that concern is gone. We've talked to analysts about both our fab capacity and our flexible capacity to stay on top of the volumes that we expect.