Intel Forum preview: Moore's Law expressed as fewer chips
Intel plans to express Moore's Law as integration of functions into fewer chips later this month at the Intel Developer Forum.
Intel is expressing Moore's Law anew as packing key technologies into fewer chips. New "Clarksfield," "Arrandale" and "Jasper Forest" processors, among others, will showcase this theme later this month at the Intel Developer Forum.
Intel Vice President Steve Smith discussed the highlights of the annual marquee Intel event that will kick off September 22 in San Francisco in a phone interview on Friday.
"Contrary to speculation that Moore's Law is slowing down or potentially dying, we're here to demonstrate that it's alive and well," Smith said. "Integration gives you a smaller, better, faster, more mobile compute platform," he said. Moore's Law, named after Intel co-founder Gordon Moore, states that the number of transistors that can be placed on an integrated circuit doubles roughly every two years.
This theme will be manifested in a number of new processors including the first mobile processor based on Intel's new Nehalem microarchitecture codenamed Clarksfield and even more highly integrated processors to follow dubbed Arrandale and Clarkdale as Intel moves to its next-generation 32-nanometer manufacturing process.
True to its rich heritage of codenames, IDF can, at times, slide into little more than a series of codename-riddled Power Point slides, with some names sounding frustratingly familiar such as Clarksfield and Clarkdale. But codenames, for better or worse, are part and parcel of IDF.
Intel codename decoder:
- Clarksfield: 45-nanometer Nehalem mobile processor integrating I/O
- Clarkdale: 32-nanometer Nehalem desktop chip integrating graphics with CPU
- Arrandale: 32-nanometer Nehalem mobile chip integrating graphics with CPU
- Moorestown: 32-nanometer system-on-chip Atom for smartphones
- Sodaville: 32-nanometer system-on-chip Atom for consumer
- Pine Trail: new Atom for Netbooks integrating graphics with CPU
- Jasper Forest: 45-nanometer, first Nehalem embedded chip for uses such as storage hardware
- Larrabee: Intel discrete graphics chip that will compete with Nvidia, AMD
- Westmere: 32-nanometer manufacturing process technology
Smith said that Intel's move to the next-generation "Westmere" 32-nanometer manufacturing process will drive even more integration next year. "We have completed development and certification of the 32-nanometer process, which means our factory is fully qualified to run the wafers. And we are actually running Westmere CPU wafers through the factory in support of our Q4 revenue production. Absolutely on track for that Q4 revenue production," he said, referring to commercial production of 32-nanometer processors.
In the more immediate future, Intel will roll out a new mobile processor based on its current 45-nanometer technology. "We just announced(the Core i5 and i7 chips for desktops), Clarksfield is the equivalent product for notebooks," Smith said. "Quad-core, 45-nanometer. Based on Nehalem technology but optimized with power management and integration of the PCI express I/O. Moving from a three-chip solution in the original Nehalem products to two chips--and that is our path going forward." I/O, or input-output, is silicon that enables a processor to talk, and shuttle data, to other parts of the system and peripheral components.
Speaking more specifically about Clarksfield integration, Smith said that "the key elements are integration of memory controller, integration of PCI Express 'gen' 2, power management." Intel will also be talking a lot about a feature called Turbo mode. "Turbo mode is extremely important. If you're not using all the cores, the cores that are not used are powered down. The cores that you are using can run at a faster clock rate with Turbo mode," Smith said.
Smith spoke about the next-generation Atom processor for Netbooks and Nettops, "Pine Trail," too. This chip will also showcase the theme of integration. "Similar integration story on the Netbook side. More capable Netbooks based on this second-generation platform. Pine Trail is optimized for Netbook and Nettop. Integrating from three chip to two chip. And we'll get some benefit from performance and power consumption from this integration."
The ultimate level of integration for Atom will come on 32-nanometer technology with Intel's system-on-chip, or SOC technology. Smith explained the path from here to there. "We have today's Atom with a discrete (separate) chipset. (Then) we have one level of integration called Pine Trail that optimizes that for Netbooks and Nettops. And then we have a system-on-a-chip initiative to put all the I/O around that so one can use a true single-chip for a consumer electronics device or into a tablet or future handheld device," he said.
While(the system-on-chip described above), a similar technology for consumer electronics devices, such as set-top boxes and TVs, is referred to as "Sodaville"--this will also be discussed.
Then there's Jasper Forest, the first Nehalem chip for the embedded market. "Another integration story. Jasper Forest is based on Nehalem but integrates the right peripherals...for embedded communications devices and high-end storage like you have in a data centers," Smith said. "Bringing Nehalem to high-end embedded designs. By doing this integration we save board space and power."
And Smith spoke about the 32-nanometer Clarkdale and Arrandale processors. "We're integrating graphics into the processor. That becomes the new expectation for a our mainstream client platforms going forward. As we move the graphics into the CPU, we get the benefit of the closer connection between the processor and the graphics and the memory that all want to be closely linked for performance and power reduction."