IDF Fall 2007, part 4-- Pat Gelsinger keynote

Pat Gelsinger talks about Intel's tick-tock development model and other aspects of the company's operation.

Pat Gelsinger worked on the Intel 286 and 386 processors and was the chief architect of the 486. Today he's a senior VP of Intel and general manager of Intel's Digital Enterprise Group.

But today his IDF keynote started out with a seemingly broader theme, covering Intel's "tick tock" development plan, platform technology, and other issues.

He opened by drawing an analogy between the aerospace industry and the microprocessor industry. If airplane development since the 747 had followed Moore's Law, one passenger jet would carry 118M people, load and unload in 12 milliseconds, and achieve 3.9 million passenger-miles per gallon. Well, that was a fairly useless analogy.

Next up was some material on the benefits of virtualization, putting Gelsinger back on Enterprise territory. A slide showed that with the benefits of virtualization, four servers can deliver 2.81 times the performance of a single server.

Gelsinger brought out John Fowler, executive VP of Sun Microsystems, to talk about Sun's use of Intel processors in servers running Sun's Solaris operating system. Fowler showed of an as-yet unannounced Intel-based four-processor server in a 2U-size rackmount enclosure, which he said will be announced soon. Of course, Sun also uses AMD processors, so Fowler didn't make a convincing case for Intel's unique contributions to its business.

The next topic was Intel's Trusted Execution Technology (abbreviated TXT). In a demo, installing a virus-compromised application into a virtual machine hosted by the Parallels software package prevents the virtual machine from running; Intel's vPro software can be used to clean up the problem. But there was no clear explanation of how this would be done. Usually the virtual-machine disk image is simply rolled back to the version before the malware was installed; vPro isn't required for this solution.

There were some interesting pointers to future technologies. PCI Express 3.0, with speeds four times faster than current PCI Express slots, will arrive in products in 2010 (PCIe 2.0 appears next year). Intel has also formed a USB 3.0 Promoters' Group to develop a follow-on for what is probably the world's most ubiquitous digital interconnect. USB 3.0 has no specific schedule yet, but it will run at "greater than ten times faster" than the current 480 Mbits/s standard.

In a rare direct comparison against AMD, Gelsinger said the forthcoming Xeon X5400, a four-core processor made up of two chips in a package and running at 3.2 GHz, will be about 4% faster than AMD's claim for the 2.5 GHz Barcelona processor due out by the end of the year.

There was a demonstration of a dual-processor Nehalem system with four cores per chip just "three weeks old"... but no performance numbers.

Finally, the processors to follow Nehalem are Westmere and Sandy Bridge, both in 32nm, in 2009 and 2010 respectively.

Back later with more...

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About the author

    Peter N. Glaskowsky is a computer architect in Silicon Valley and a technology analyst for the Envisioneering Group. He has designed chip- and board-level products in the defense and computer industries, managed design teams, and served as editor in chief of the industry newsletter "Microprocessor Report." He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure.

     

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