Sun: UltraSparc IV+ doubles server oomph
Sun Microsystems on Tuesday will detail "Panther," which promises more high-speed cache memory and higher clock speeds.
- Shankland covered the tech industry for more than 25 years and was a science writer for five years before that. He has deep expertise in microprocessors, digital photography, computer hardware and software, internet standards, web technology, and more.
Like the current UltraSparc IV, the UltraSparc IV+ will have two processing engines, or cores, on a single slice of silicon. Unlike it, though, Panther will be built with a more advanced manufacturing process that allows more high-speed cache memory and higher clock speeds.
The UltraSparc IV+ is due to arrive in mid-2005, roughly a year after the UltraSparc IV, said Dale Greenley, director of engineering for the new chip. It will run at an initial speed of 1.8GHz--with models faster than 2GHz planned later--compared with 1.2GHz for today's fastest UltraSparc IV models, he said.
Sun plans to detail the new chips at the Fall Processor Forum in San Jose, Calif.
Even though Sun's fortunes have begun to turn around from a three-year slump, the UltraSparc family still faces several challenges. IBM offers its Power processors, not just running its own AIX version of Unix but now also with Red Hat and Novell's versions of Linux. Hewlett-Packard teamed with Intel to produce the Itanium family. And x86 chips such as Intel's Xeon and Advanced Micro Devices' Opteron are steadily growing more powerful.
Sun has adopted a dual-chip strategy, warming up to x86 in general and Opteron especially. And although Sun canceled its UltraSparc V, it continues to develop new Sparc models code-named Niagara and Rock while relying on a partnership with Fujitsu for other high-end Sparc models.
Sun's long-term plans extend four years into the future. Niagara servers are due to arrive in 2006, as are systems from the Fujitsu collaboration. Rock servers are due in 2008.
The UltraSparc IV+, like its predecessors, is built by Texas Instruments, but it uses a new process. The features on UltraSparc IV measure 130 nanometers, or 130 billionths of a meter, but the IV+ is built with 90-nanometer features. That allows more circuitry to be packed onto the chip--an increase from 60 million to nearly 300 million, Greenley said.
Most of that new circuitry is memory. Where the UltraSparc IV had 16MB of cache memory packaged separately from the chip--8MB for each processor core--the IV+ will have 2MB directly on the chip shared by the two cores and 32MB packaged separately, Greenley said. On-chip cache is faster than cache packaged separately.
To help keep up with the faster speeds, the UltraSparc IV+ can "prefetch" instructions better, storing the tasks it projects it will likely need to accomplish soon, Greenley said. The new chip has eight pathways for transferring these instructions to the chip compared with one in the UltraSparc IV.
In addition, the new prefetch pathways for instructions and the existing pathways for data are protected by error correction technology that can detect when a one has been flipped to a zero or vice-versa.
Such "bit flipping" problems worsen as chip features shrink because a single cosmic ray can flip two pathways' bits simultaneously, an effect that can escape the attention of error-correction technology only looking for a single flip. "A single cosmic ray has potential to flip multiple bits because (the pathways) are so close together," but Sun sidesteps the problem by making sure error detection systems check pathways that are relatively far apart, Greenley said.
Current UltraSparc III and IV systems using Uniboard processor boards can be upgraded with IV+ chips, Greenley said.