Spansion, created from a flash memory joint venture started by Advanced Micro Devices and Fujitsu, says that the "charge-trapping" technology that underlies its MirrorBit and Ornand flash chips provides a path for the industry to continue to shrink the size--and hence increase the performance--of flash chips.
Spansion already makes flash chips that rely on charge trapping, which is similar but slightly different than conventional "floating gate" flash. Now it has begun a campaign to license some of its ideas to other manufacturers, Spansion CEO Bertrand Cambou told CNET News.com.
"Samsung, Toshiba, and Hynix have all announced publicly that they have a strong interest in charge trapping," Cambou said. "We have some fundamental patents for it. It is not an easy technology...We have been working on it for years."
Charge trapping, moreover, can be used in NOR flash chips, a smaller market historically dominated by Intel and Spansion, and NAND flash chips, found inside phones and MP3 players. Although AMD started making charge-trapping chips back in 2002, a lot of the basic technology comes from Israel's Saifun Semiconductors, which Spansion bought in October for $328 million.
If Spansion can pull this off, it could turn into a financial boost for the company, which. In the third quarter, Spansion reported a $72 million net loss on revenue of $611 million. Chipmakers typically are loath to license technology, particularly from their direct competitors, but it occurs. Toshiba has generated significant revenue from its technology formulas for NAND.
NAND patents are valuable because of the still-growing demand for consumer electronics and phones. Although NAND prices swing up and down, NAND volumes continue to increase annually. In fact, many chipmakers now upgrade their factories to accommodate NAND volumes first. In the past, many launched new factories with DRAM or other chips. Some NAND makers are now trying to push their products into notebooks and blade servers, displacing hard drives.
"NAND is the killer app," Mike Splinter, CEO of Applied Materials, which makes semiconductor equipment, said in a recent interview.
Most executives and scientists in the booming flash memory market say that the technology is headed toward acrisis. Simply put, manufacturers won't be able to continue to shrink their chips without major architectural changes. Without shrinking, chipmakers can't cut costs, drive up performance, or increase volumes with the same underlying economics as the past.
What is charge trapping? The memory cells in conventional floating gate flash consist of a sandwich of materials: Polysilicon is encased between two layers of silicon dioxide, or glass. Once an electron is trapped in a cell, it will stay inside for 10 years, which is why your pictures stay on memory cards until you deliberately erase them.
By contrast, in charge trapping, the middle section consists of an oxide-nitride-oxide layer. Charge trapping is also known in the industry as Nitride, or ONO.
"Once you get down to a certain cell size, you have real problems with conventional flash," said Jim Handy, president of analysis firm Objective Analysis. "It seems like at 45 or 35 nanometer conventional flash starts to run into a limit. They won't be able to use the same materials."
Forty five-nanometer flash chips are due in the next one to two years. Some types of nonvolatile memory already having shrinkage problems. MRAM, a type of memory supported by Freescale Semiconductor and IBM, may not get beyond thein widespread use today.
The big problem for Spansion will lay in getting the industry to go along. Everyone has their own ideas for the future of memory, and at this point, it's far from clear which will survive. Some of the competing ideas include
Charge trapping has two significant advantages over those listed above, Cambou asserted. One, people already know how to make it, which removes some of the risk. Two, lab tests show that charge-trapping memory can be shrunk.
"We have (laboratory) cells that are functional at 20 nanometers," he said. "If we can shrink it, we can be the cheapest." The figures refer to the average feature size on chips. A nanometer is a billionth of a meter. The smaller the features, the better the performance and cheaper the cost, generally.
Still, manufacturing of 20-nanometer memory isn't expected to happen until 2012 or later.
Charge-trapping memory cells, Cambou added, are also small compared with other types of memory cells on the same manufacturing dimensions, which further cuts costs.
"If your cell size is big, that is a niche," he said. "Charge trapping is going to be the big technology in the next 10 years."