Paolo Gargini, director of technology strategy, unveiled new research into vertically stacked chips that could reduce the distance signals have to travel across multicore processors. Like most of Intel's manufacturing research, the company hasn't settled on this approach as a cure-all to the challenge of extending, but it is eyeing this new research as an option for future chip packaging techniques.
Intel revealed a few details about itsthis week for the first time. Tigerton, Cloverton and Kentsfield will all have four processor cores, but they are essentially two dual-core chips held together in what's called a multichip package. This technique allows Intel to get the chips out into the market more quickly than a design with four integrated cores, but the multichip package means signals have to leave one core and travel outside the silicon die to get to a core on the other chip, hurting performance.
At some point in the future, Intel believes it will be able to essentially fold a multichip package in half and connect the two dies directly to one another, said Rob Willoner, a technology analyst at Intel. More research needs to be done on sophisticated interconnects that can accommodate that type of design, but Intel hasin this area.
Intel has also worked on stacking memory chips on top of processors, a technique used to build the Hermon and Manitoba mobile phone processors.
Gargini alsomanufacturing technology is right on schedule, just as the company is moving ahead with the new 65nm technology used to build the Core Duo processor. In the third quarter of this year, Intel will be shipping more 65nm chips than 90nm chips, and it will introduce 45nm chips by the end of next year, he said.