The Santa Clara, Calif.-based chipmaker announced Monday that it has made static random access memory (SRAM) cells, a type of memory, with the 65-nanometer process and will start to mass-manufacture chips on the process in 2005. The nanometer figure refers to the average size of features on chips produced with the process. Most PC microprocessors on the market today are made on the 130-nanometer process, and manufacturers are just starting to produce 90-nanometer chips now. (A nanometer is a billionth of meter.)
Reducing the size of the chip improves performance, reduces costs and can potentially cut energy consumption. In a nutshell, electrons have a shorter commute in 65-nanometer chips, so performance goes up. The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.
"You can get a 40 (percent) to 50 percent increase in clock speed with no further improvements," said Mark Bohr, Intel senior fellow and director of process architecture and integration.
More transistors can be inserted into chips as well, which also boosts performance. Moore's Law dictates that the number of transistors doubles on a given chip with biennial manufacturing advances. While chipmakers often don't automatically double transistor count, they do increase it substantially so that new features can be added to the silicon.
Meanwhile, costs go down, because more individual chips can be popped out of the same. The experimental SRAM cells Intel produced when developing the 90-nanometer process measured 1 square micron, Bohr said. The 65-nanometer cells revealed this week measure 0.57 square microns. (SRAM cells are often used as test vehicles for new manufacturing processes.)
Costs are further cut by the fact that Intel will be able to reuse about 70 percent of the equipment currently relied on to produce 90-nanometer chips, including lithography machines that "draw" circuits with light with a wavelength of 193 nanometers. The light beam is actually much bigger than the circuits but can be used to draw fine lines through attenuation and other techniques, Bohr said.
Energy gains can be tougher to establish. Although energy consumption technically should decrease with more refined processes, manufacturers typically boost the performance on chips made on new processes, which tends to erase energy conservation., the unintentional dissipation of electricity, among other phenomena, can also inadvertently raise memory consumption. Leakage, in fact, will increase on 65-nanometer chips, Bohr said, but the impact can be minimized through design.
To reduce energy consumption, the 65-nanometer chips will containand a low-k (low capacitance) dielectric layer, which, in addition to reducing power consumption, increases speed. Both of these features are in Intel's 90-nanometer chips.
Bohr also said the 65-nanometer chips would not includeor . Those technologies may be included in the 45-nanometer chips coming in 2007.
The 65-nanometer chips will not include the IBM-touted silicon-on-insulator technology, either. "We have not seen any significant performance advantages with SOI," Bohr said.
Manufacturing advances are becoming increasingly difficult to achieve, according to many engineers and executives. Both Intel and Advanced Micro Devices had to delay the release of 90-nanometer chips, and a number of companies had major problems with the shift to 130-nanometer manufacturing in 2001. Still, Bohr said Intel will likely be able to keep up with Moore's Law for another decade.
In, Intel President Paul Otellini said the company has also produced wafers on the 65-nanometer process (which produced the chips Bohr spoke about Monday), transistors on the 45-nanometer process and prototype transistors for the 32- and 22-nanometer processes. That will take the company to 2011.