Intel pitching Silverthorne, Itanium at ISSCC
World's largest chipmaker plans to present technical papers on two of its more interesting designs, the low-power Silverthorne chip and a quad-core Itanium processor, during the ISSCC conference this week.
Intel is expected to shed light on its processor of the future this week as it plugs along with another design that was once supposed to be its processor of the future.
The chip industry's finest minds will be descending on San Francisco this week for the International Solid State Circuits Conference, and Intel plans to present 14 papers highlighting some of its recent work, said Justin Rattner, Intel's chief technology officer and head of Intel Labs. Chief among them will be its , Intel's latest plan to infiltrate the world of handheld devices.
"This is the smallest (x86 instruction set) processor we've built in the last 15 to 17 years," Rattner said, speaking of Silverthorne in a briefing for reporters prior to the conference. Silverthorne is expected to arrive in the second quarter in so-called mobile Internet devices, but it's really a stepping stone for Intel toward a lower-power future.
The ultimate goal for Intel is to design a chip that will fit into the next generation of mobile devices and smartphones, carving out a niche for PC software and programming techniques in a world dominated by chip designer ARM and its partners, such as Texas Instruments and Samsung. With a power consumption range between half a watt and two watts, Silverthorneoccupied by those chips. But it can run any piece of at the performance level achieved by one of Intel's 5-year-old Pentium M processors.
Silverthorne is a departure from the rest of Intel's designs in that, as opposed to the out-of-order design used in just about every other chip the company makes. That means pretty much what it sounds like; in-order chips have to process tasks in a defined order, but out-of-order chips can process tasks separately and reassemble a finished product later. Out-of-order means better performance, in-order generally means lower power consumption.
The chip also incorporates a new low-power state, allowing it to essentially shut down in between processing tasks and limit power consumption. And just in case the software industry starts producing more multithreaded applications, Intel added an old friend, hyperthreading, to Silverthorne. Hyperthreading allows Silverthorne to present itself as a dual-core chip to software, even though it only has one physical processing core.
While Silverthorne is considered a huge part of Intel's future, Tukwilla, the other major design being presented at ISSCC, is a remmant of Intel's past. Tukwilla will be the next version of the Itanium processor, which Intel once thought could take over the server industry but has been relegated instead to a high-end niche.
Still, that's a powerful niche. Tukwilla will be the first quad-core Itanium processor, and it will use a whopping 30MBs of cache memory. This is going to be a high-performance (read: expensive) chip for high-end servers, and it will also be one of Intel's first chips that borrows design techniques employed by Intel's rival, Advanced Micro Devices, to great effect.
Tukwilla will use point-to-point connection technology that Intel calls Quickpath to directly link processing cores together. AMD introduced this way back in 2003 with its Opteron processor, and it delivers a significant boost in performance as the chip industry moves into the multicore era. Intel's current designs required signals traveling between two different processor cores to leave, then re-enter, the chip. Quickpath lets those signals stay on the chip, allowing them to travel a shorter distance at higher speeds. That's good.
Tukwilla will also use an integrated memory controller, which is a similar concept. Integrated memory controllers, as the name implies, are integrated directly onto the chip. This allows this vital link between the processor and the main memory to run at the speed of the chip, rather than the slower speeds necessitated by the front-side bus design used by Intel's chips.
Intel eventually plans to bring Quickpath and integrated memory controllers down to its Xeon line of server processors, which go into the vast majority of the world's servers. That will arrive with the Nehalem generation of chips, due out later in 2008.
Intel's researchers also plan to present papers in other areas, such as wireless technologies and memory research. The company has been working on radios that can employ multiple protocols, from Wi-Fi and WiMax to even cellular standards, and it plans to highlight some research in this area. The company is also investigating phase-change memory, one possible way to prepare for the end of Moore's Law by discovering ways to represent the fundamental zeros and ones of computing with something other than a transistor.
These presentations are not for the faint of heart. An electrical engineering degree would be very helpful in deciphering the papers, although not exactly required. We'll be on hand during the week to highlight some of the more interesting presentations, especially Silverthorne, which is a key part of Intel's future plans.